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alexdeucheralexdeucher
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drm/amdgpu/gfx11: don't read registers in mqd init
Just use the default values. There's not need to get the value from hardware and it could cause problems if we do that at runtime and gfxoff is active. Reviewed-by: Mukul Joshi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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+32
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‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

Lines changed: 32 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,23 @@
6262
#define regPC_CONFIG_CNTL_1 0x194d
6363
#define regPC_CONFIG_CNTL_1_BASE_IDX 1
6464

65+
#define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
66+
#define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
67+
#define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
68+
#define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
69+
#define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000
70+
#define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
71+
#define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
72+
73+
#define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
74+
#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
75+
#define regCP_MQD_CONTROL_DEFAULT 0x00000100
76+
#define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
77+
#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
78+
#define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
79+
#define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
80+
#define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
81+
6582
MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
6683
MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
6784
MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
@@ -3965,7 +3982,7 @@ static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
39653982
if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
39663983
priority = 1;
39673984

3968-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3985+
tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
39693986
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
39703987
mqd->cp_gfx_hqd_queue_priority = tmp;
39713988
}
@@ -3987,22 +4004,22 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
39874004
mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
39884005

39894006
/* set up mqd control */
3990-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
4007+
tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
39914008
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
39924009
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
39934010
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
39944011
mqd->cp_gfx_mqd_control = tmp;
39954012

39964013
/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3997-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
4014+
tmp = regCP_GFX_HQD_VMID_DEFAULT;
39984015
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
39994016
mqd->cp_gfx_hqd_vmid = 0;
40004017

40014018
/* set up gfx queue priority */
40024019
gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop);
40034020

40044021
/* set up time quantum */
4005-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
4022+
tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
40064023
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
40074024
mqd->cp_gfx_hqd_quantum = tmp;
40084025

@@ -4024,7 +4041,7 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
40244041

40254042
/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
40264043
rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
4027-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
4044+
tmp = regCP_GFX_HQD_CNTL_DEFAULT;
40284045
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
40294046
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
40304047
#ifdef __BIG_ENDIAN
@@ -4033,7 +4050,7 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
40334050
mqd->cp_gfx_hqd_cntl = tmp;
40344051

40354052
/* set up cp_doorbell_control */
4036-
tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
4053+
tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
40374054
if (prop->use_doorbell) {
40384055
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
40394056
DOORBELL_OFFSET, prop->doorbell_index);
@@ -4045,7 +4062,7 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
40454062
mqd->cp_rb_doorbell_control = tmp;
40464063

40474064
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4048-
mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
4065+
mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
40494066

40504067
/* active the queue */
40514068
mqd->cp_gfx_hqd_active = 1;
@@ -4131,14 +4148,14 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
41314148
mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
41324149

41334150
/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4134-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
4151+
tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
41354152
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
41364153
(order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
41374154

41384155
mqd->cp_hqd_eop_control = tmp;
41394156

41404157
/* enable doorbell? */
4141-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
4158+
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
41424159

41434160
if (prop->use_doorbell) {
41444161
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
@@ -4167,7 +4184,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
41674184
mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
41684185

41694186
/* set MQD vmid to 0 */
4170-
tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
4187+
tmp = regCP_MQD_CONTROL_DEFAULT;
41714188
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
41724189
mqd->cp_mqd_control = tmp;
41734190

@@ -4177,7 +4194,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
41774194
mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
41784195

41794196
/* set up the HQD, this is similar to CP_RB0_CNTL */
4180-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
4197+
tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
41814198
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
41824199
(order_base_2(prop->queue_size / 4) - 1));
41834200
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
@@ -4203,7 +4220,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
42034220
tmp = 0;
42044221
/* enable the doorbell if requested */
42054222
if (prop->use_doorbell) {
4206-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
4223+
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
42074224
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
42084225
DOORBELL_OFFSET, prop->doorbell_index);
42094226

@@ -4218,17 +4235,17 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
42184235
mqd->cp_hqd_pq_doorbell_control = tmp;
42194236

42204237
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4221-
mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
4238+
mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
42224239

42234240
/* set the vmid for the queue */
42244241
mqd->cp_hqd_vmid = 0;
42254242

4226-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
4243+
tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
42274244
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
42284245
mqd->cp_hqd_persistent_state = tmp;
42294246

42304247
/* set MIN_IB_AVAIL_SIZE */
4231-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
4248+
tmp = regCP_HQD_IB_CONTROL_DEFAULT;
42324249
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
42334250
mqd->cp_hqd_ib_control = tmp;
42344251

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