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torvaldstorvalds
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Merge tag 'spi-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "The diffstat for this release is dominated by the new Airoha driver, mainly as a result of this being a generally quite quiet release. There were a couple of cleanups in the core but nothing substantial, the updates here are almost all driver specific ones. - Support for multi-word mode in the OMAP2 McSPI driver - Overhaul of the PXA2xx driver, mostly API updates - A number of DT binding conversions - Support for Airoha NAND controllers, Cirrus Logic CS35L56, Mobileye EYEQ5 and Renesas R8A779H0" * tag 'spi-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (87 commits) spi: dw: Bail out early on unsupported target mode spi: Remove unneded check for orig_nents MAINTAINERS: repair file entry in AIROHA SPI SNFI DRIVER spi: pxa2xx: Drop the stale entry in documentation TOC spi: pxa2xx: Don't provide struct chip_data for others spi: pxa2xx: Remove timeout field from struct chip_data spi: pxa2xx: Remove DMA parameters from struct chip_data spi: pxa2xx: Drop struct pxa2xx_spi_chip spi: pxa2xx: Don't use "proxy" headers spi: pxa2xx: Remove outdated documentation spi: pxa2xx: Move contents of linux/spi/pxa2xx_spi.h to a local one spi: pxa2xx: Provide num-cs for Sharp PDAs via device properties spi: pxa2xx: Allow number of chip select pins to be read from property spi: dt-bindings: ti,qspi: convert to dtschema spi: bitbang: Add missing MODULE_DESCRIPTION() spi: bitbang: Use NSEC_PER_*SEC rather than hard coding spi: dw: Drop default number of CS setting spi: dw: Convert dw_spi::num_cs to u32 spi: dw: Add a number of native CS auto-detection spi: dw: Convert to using BITS_TO_BYTES() macro ...
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‎Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/airoha,en7581-snand.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SPI-NAND flash controller for Airoha ARM SoCs
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maintainers:
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- Lorenzo Bianconi <[email protected]>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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const: airoha,en7581-snand
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reg:
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items:
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- description: spi base address
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- description: nfi2spi base address
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: spi
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/en7523-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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spi@1fa10000 {
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compatible = "airoha,en7581-snand";
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reg = <0x0 0x1fa10000 0x0 0x140>,
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<0x0 0x1fa11000 0x0 0x160>;
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clocks = <&scuclk EN7523_CLK_SPI>;
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clock-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <2>;
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};
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};
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};

‎Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

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- items:
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- enum:
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- amd,pensando-elba-qspi
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- ti,k2g-qspi
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- ti,am654-ospi
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- intel,lgm-qspi
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- xlnx,versal-ospi-1.0
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- intel,socfpga-qspi
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- mobileye,eyeq5-ospi
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- starfive,jh7110-qspi
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- ti,am654-ospi
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- ti,k2g-qspi
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- xlnx,versal-ospi-1.0
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- const: cdns,qspi-nor
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- const: cdns,qspi-nor
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- reg
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- interrupts
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- clocks
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- cdns,fifo-depth
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- cdns,fifo-width
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- cdns,trigger-address
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- '#address-cells'

‎Documentation/devicetree/bindings/spi/marvell,armada-3700-spi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/marvell,armada-3700-spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 3700 SPI Controller
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description:
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The SPI controller on Marvell Armada 3700 SoC.
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maintainers:
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- Kousik Sanagavarapu <[email protected]>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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const: marvell,armada-3700-spi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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num-cs:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi0: spi@10600 {
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compatible = "marvell,armada-3700-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10600 0x5d>;
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clocks = <&nb_perih_clk 7>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <4>;
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};
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...

‎Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml

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- renesas,msiof-r8a779a0 # R-Car V3U
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- renesas,msiof-r8a779f0 # R-Car S4-8
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- renesas,msiof-r8a779g0 # R-Car V4H
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- renesas,msiof-r8a779h0 # R-Car V4M
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- const: renesas,rcar-gen4-msiof # generic R-Car Gen4
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# compatible device
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- items:

‎Documentation/devicetree/bindings/spi/spi-armada-3700.txt

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‎Documentation/devicetree/bindings/spi/ti,qspi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/ti,qspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI QSPI controller
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maintainers:
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- Kousik Sanagavarapu <[email protected]>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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enum:
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- ti,am4372-qspi
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- ti,dra7xxx-qspi
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reg:
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items:
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- description: base registers
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- description: mapped memory
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reg-names:
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items:
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- const: qspi_base
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- const: qspi_mmap
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: fck
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interrupts:
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maxItems: 1
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num-cs:
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minimum: 1
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maximum: 4
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default: 1
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ti,hwmods:
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description:
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Name of the hwmod associated to the QSPI. This is for legacy
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platforms only.
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$ref: /schemas/types.yaml#/definitions/string
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deprecated: true
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syscon-chipselects:
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description:
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Handle to system control region containing QSPI chipselect register
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and offset of that register.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to system control register
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- description: register offset
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spi-max-frequency:
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description: Maximum SPI clocking speed of the controller in Hz.
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/dra7.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@4b300000 {
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compatible = "ti,dra7xxx-qspi";
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reg = <0x4b300000 0x100>,
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<0x5c000000 0x4000000>;
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reg-names = "qspi_base", "qspi_mmap";
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syscon-chipselects = <&scm_conf 0x558>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
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clock-names = "fck";
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num-cs = <4>;
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spi-max-frequency = <48000000>;
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interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
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};
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...

‎Documentation/devicetree/bindings/spi/ti_qspi.txt

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‎Documentation/spi/index.rst

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spi-summary
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spidev
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butterfly
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pxa2xx
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spi-lm70llp
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spi-sc18is602
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