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394 | 394 | };
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395 | 395 |
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396 | 396 | sdma2: dma-controller@302c0000 {
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397 |
| - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; |
| 397 | + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; |
398 | 398 | reg = <0x302c0000 0x10000>;
|
399 | 399 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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400 | 400 | clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
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|
405 | 405 | };
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406 | 406 |
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407 | 407 | sdma3: dma-controller@302b0000 {
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408 |
| - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; |
| 408 | + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; |
409 | 409 | reg = <0x302b0000 0x10000>;
|
410 | 410 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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411 | 411 | clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
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|
737 | 737 | };
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738 | 738 |
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739 | 739 | sdma1: dma-controller@30bd0000 {
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740 |
| - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; |
| 740 | + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; |
741 | 741 | reg = <0x30bd0000 0x10000>;
|
742 | 742 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
743 | 743 | clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
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|
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