Skip to content

Commit e35b07a

Browse files
geertupalmer-dabbelt
authored andcommitted
riscv: dts: microchip: mpfs: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Tested-by: Conor Dooley <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
1 parent 9e85020 commit e35b07a

File tree

1 file changed

+16
-15
lines changed

1 file changed

+16
-15
lines changed

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -158,18 +158,18 @@
158158
cache-size = <2097152>;
159159
cache-unified;
160160
interrupt-parent = <&plic>;
161-
interrupts = <1 2 3>;
161+
interrupts = <1>, <2>, <3>;
162162
reg = <0x0 0x2010000 0x0 0x1000>;
163163
};
164164

165165
clint@2000000 {
166166
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
167167
reg = <0x0 0x2000000 0x0 0xC000>;
168-
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
169-
&cpu1_intc 3 &cpu1_intc 7
170-
&cpu2_intc 3 &cpu2_intc 7
171-
&cpu3_intc 3 &cpu3_intc 7
172-
&cpu4_intc 3 &cpu4_intc 7>;
168+
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
169+
<&cpu1_intc 3>, <&cpu1_intc 7>,
170+
<&cpu2_intc 3>, <&cpu2_intc 7>,
171+
<&cpu3_intc 3>, <&cpu3_intc 7>,
172+
<&cpu4_intc 3>, <&cpu4_intc 7>;
173173
};
174174

175175
plic: interrupt-controller@c000000 {
@@ -178,19 +178,20 @@
178178
#address-cells = <0>;
179179
#interrupt-cells = <1>;
180180
interrupt-controller;
181-
interrupts-extended = <&cpu0_intc 11
182-
&cpu1_intc 11 &cpu1_intc 9
183-
&cpu2_intc 11 &cpu2_intc 9
184-
&cpu3_intc 11 &cpu3_intc 9
185-
&cpu4_intc 11 &cpu4_intc 9>;
181+
interrupts-extended = <&cpu0_intc 11>,
182+
<&cpu1_intc 11>, <&cpu1_intc 9>,
183+
<&cpu2_intc 11>, <&cpu2_intc 9>,
184+
<&cpu3_intc 11>, <&cpu3_intc 9>,
185+
<&cpu4_intc 11>, <&cpu4_intc 9>;
186186
riscv,ndev = <186>;
187187
};
188188

189189
dma@3000000 {
190190
compatible = "sifive,fu540-c000-pdma";
191191
reg = <0x0 0x3000000 0x0 0x8000>;
192192
interrupt-parent = <&plic>;
193-
interrupts = <23 24 25 26 27 28 29 30>;
193+
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
194+
<30>;
194195
#dma-cells = <1>;
195196
};
196197

@@ -254,7 +255,7 @@
254255
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
255256
reg = <0x0 0x20008000 0x0 0x1000>;
256257
interrupt-parent = <&plic>;
257-
interrupts = <88 89>;
258+
interrupts = <88>, <89>;
258259
clocks = <&clkcfg 6>;
259260
max-frequency = <200000000>;
260261
status = "disabled";
@@ -264,7 +265,7 @@
264265
compatible = "cdns,macb";
265266
reg = <0x0 0x20110000 0x0 0x2000>;
266267
interrupt-parent = <&plic>;
267-
interrupts = <64 65 66 67>;
268+
interrupts = <64>, <65>, <66>, <67>;
268269
local-mac-address = [00 00 00 00 00 00];
269270
clocks = <&clkcfg 4>, <&clkcfg 2>;
270271
clock-names = "pclk", "hclk";
@@ -277,7 +278,7 @@
277278
compatible = "cdns,macb";
278279
reg = <0x0 0x20112000 0x0 0x2000>;
279280
interrupt-parent = <&plic>;
280-
interrupts = <70 71 72 73>;
281+
interrupts = <70>, <71>, <72>, <73>;
281282
local-mac-address = [00 00 00 00 00 00];
282283
clocks = <&clkcfg 5>, <&clkcfg 2>;
283284
status = "disabled";

0 commit comments

Comments
 (0)