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danvetdanvet
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Merge tag 'drm-intel-fixes-2023-03-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v6.3-rc4: - Fix an MTL workaround - Fix fbdev obj locking before vma pin - Fix state inheritance tracking in initial commit - Fix missing GuC error capture codes - Fix missing debug object activation - Fix uc init late order relative to probe error injection - Fix perf limit reasons formatting - Fix vblank timestamp update on seamless M/N changes Signed-off-by: Daniel Vetter <[email protected]> From: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 9b5dbf6 + 22aa20e commit e37fef7

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13 files changed

+88
-72
lines changed

13 files changed

+88
-72
lines changed

‎drivers/gpu/drm/i915/display/intel_crtc.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -683,6 +683,14 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
683683
*/
684684
intel_vrr_send_push(new_crtc_state);
685685

686+
/*
687+
* Seamless M/N update may need to update frame timings.
688+
*
689+
* FIXME Should be synchronized with the start of vblank somehow...
690+
*/
691+
if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
692+
intel_crtc_update_active_timings(new_crtc_state);
693+
686694
local_irq_enable();
687695

688696
if (intel_vgpu_active(dev_priv))

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5145,6 +5145,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
51455145
* only fields that are know to not cause problems are preserved. */
51465146

51475147
saved_state->uapi = crtc_state->uapi;
5148+
saved_state->inherited = crtc_state->inherited;
51485149
saved_state->scaler_state = crtc_state->scaler_state;
51495150
saved_state->shared_dpll = crtc_state->shared_dpll;
51505151
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;

‎drivers/gpu/drm/i915/display/intel_dmc.c

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -384,15 +384,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
384384
}
385385
}
386386

387-
static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
387+
static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
388388
{
389389
enum pipe pipe;
390390

391-
if (DISPLAY_VER(i915) < 13)
392-
return;
393-
394391
/*
395-
* Wa_16015201720:adl-p,dg2, mtl
392+
* Wa_16015201720:adl-p,dg2
396393
* The WA requires clock gating to be disabled all the time
397394
* for pipe A and B.
398395
* For pipe C and D clock gating needs to be disabled only
@@ -408,6 +405,25 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
408405
PIPEDMC_GATING_DIS, 0);
409406
}
410407

408+
static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
409+
{
410+
/*
411+
* Wa_16015201720
412+
* The WA requires clock gating to be disabled all the time
413+
* for pipe A and B.
414+
*/
415+
intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
416+
MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
417+
}
418+
419+
static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
420+
{
421+
if (DISPLAY_VER(i915) >= 14 && enable)
422+
mtl_pipedmc_clock_gating_wa(i915);
423+
else if (DISPLAY_VER(i915) == 13)
424+
adlp_pipedmc_clock_gating_wa(i915, enable);
425+
}
426+
411427
void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
412428
{
413429
if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))

‎drivers/gpu/drm/i915/display/intel_fbdev.c

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
210210
bool prealloc = false;
211211
void __iomem *vaddr;
212212
struct drm_i915_gem_object *obj;
213+
struct i915_gem_ww_ctx ww;
213214
int ret;
214215

215216
mutex_lock(&ifbdev->hpd_lock);
@@ -283,13 +284,24 @@ static int intelfb_create(struct drm_fb_helper *helper,
283284
info->fix.smem_len = vma->size;
284285
}
285286

286-
vaddr = i915_vma_pin_iomap(vma);
287-
if (IS_ERR(vaddr)) {
288-
drm_err(&dev_priv->drm,
289-
"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
290-
ret = PTR_ERR(vaddr);
291-
goto out_unpin;
287+
for_i915_gem_ww(&ww, ret, false) {
288+
ret = i915_gem_object_lock(vma->obj, &ww);
289+
290+
if (ret)
291+
continue;
292+
293+
vaddr = i915_vma_pin_iomap(vma);
294+
if (IS_ERR(vaddr)) {
295+
drm_err(&dev_priv->drm,
296+
"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
297+
ret = PTR_ERR(vaddr);
298+
continue;
299+
}
292300
}
301+
302+
if (ret)
303+
goto out_unpin;
304+
293305
info->screen_base = vaddr;
294306
info->screen_size = vma->size;
295307

‎drivers/gpu/drm/i915/gt/intel_gt.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -737,12 +737,12 @@ int intel_gt_init(struct intel_gt *gt)
737737
if (err)
738738
goto err_gt;
739739

740-
intel_uc_init_late(&gt->uc);
741-
742740
err = i915_inject_probe_error(gt->i915, -EIO);
743741
if (err)
744742
goto err_gt;
745743

744+
intel_uc_init_late(&gt->uc);
745+
746746
intel_migrate_init(&gt->migrate, gt);
747747

748748
goto out_fw;

‎drivers/gpu/drm/i915/gt/intel_gt_pm.c

Lines changed: 0 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -21,31 +21,10 @@
2121
#include "intel_rc6.h"
2222
#include "intel_rps.h"
2323
#include "intel_wakeref.h"
24-
#include "intel_pcode.h"
2524
#include "pxp/intel_pxp_pm.h"
2625

2726
#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
2827

29-
static void mtl_media_busy(struct intel_gt *gt)
30-
{
31-
/* Wa_14017073508: mtl */
32-
if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
33-
gt->type == GT_MEDIA)
34-
snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
35-
PCODE_MBOX_GT_STATE_MEDIA_BUSY,
36-
PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
37-
}
38-
39-
static void mtl_media_idle(struct intel_gt *gt)
40-
{
41-
/* Wa_14017073508: mtl */
42-
if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
43-
gt->type == GT_MEDIA)
44-
snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
45-
PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
46-
PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
47-
}
48-
4928
static void user_forcewake(struct intel_gt *gt, bool suspend)
5029
{
5130
int count = atomic_read(&gt->user_wakeref);
@@ -93,9 +72,6 @@ static int __gt_unpark(struct intel_wakeref *wf)
9372

9473
GT_TRACE(gt, "\n");
9574

96-
/* Wa_14017073508: mtl */
97-
mtl_media_busy(gt);
98-
9975
/*
10076
* It seems that the DMC likes to transition between the DC states a lot
10177
* when there are no connected displays (no active power domains) during
@@ -145,9 +121,6 @@ static int __gt_park(struct intel_wakeref *wf)
145121
GEM_BUG_ON(!wakeref);
146122
intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
147123

148-
/* Wa_14017073508: mtl */
149-
mtl_media_idle(gt);
150-
151124
return 0;
152125
}
153126

‎drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -580,7 +580,7 @@ static bool perf_limit_reasons_eval(void *data)
580580
}
581581

582582
DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
583-
perf_limit_reasons_clear, "%llu\n");
583+
perf_limit_reasons_clear, "0x%llx\n");
584584

585585
void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
586586
{

‎drivers/gpu/drm/i915/gt/intel_rc6.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -486,6 +486,7 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
486486
static bool rc6_supported(struct intel_rc6 *rc6)
487487
{
488488
struct drm_i915_private *i915 = rc6_to_i915(rc6);
489+
struct intel_gt *gt = rc6_to_gt(rc6);
489490

490491
if (!HAS_RC6(i915))
491492
return false;
@@ -502,6 +503,13 @@ static bool rc6_supported(struct intel_rc6 *rc6)
502503
return false;
503504
}
504505

506+
if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
507+
gt->type == GT_MEDIA) {
508+
drm_notice(&i915->drm,
509+
"Media RC6 disabled on A step\n");
510+
return false;
511+
}
512+
505513
return true;
506514
}
507515

‎drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1571,6 +1571,27 @@ int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf,
15711571

15721572
#endif //CONFIG_DRM_I915_CAPTURE_ERROR
15731573

1574+
static void guc_capture_find_ecode(struct intel_engine_coredump *ee)
1575+
{
1576+
struct gcap_reg_list_info *reginfo;
1577+
struct guc_mmio_reg *regs;
1578+
i915_reg_t reg_ipehr = RING_IPEHR(0);
1579+
i915_reg_t reg_instdone = RING_INSTDONE(0);
1580+
int i;
1581+
1582+
if (!ee->guc_capture_node)
1583+
return;
1584+
1585+
reginfo = ee->guc_capture_node->reginfo + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE;
1586+
regs = reginfo->regs;
1587+
for (i = 0; i < reginfo->num_regs; i++) {
1588+
if (regs[i].offset == reg_ipehr.reg)
1589+
ee->ipehr = regs[i].value;
1590+
else if (regs[i].offset == reg_instdone.reg)
1591+
ee->instdone.instdone = regs[i].value;
1592+
}
1593+
}
1594+
15741595
void intel_guc_capture_free_node(struct intel_engine_coredump *ee)
15751596
{
15761597
if (!ee || !ee->guc_capture_node)
@@ -1612,6 +1633,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
16121633
list_del(&n->link);
16131634
ee->guc_capture_node = n;
16141635
ee->guc_capture = guc->capture;
1636+
guc_capture_find_ecode(ee);
16151637
return;
16161638
}
16171639
}

‎drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -11,20 +11,9 @@
1111

1212
static bool __guc_rc_supported(struct intel_guc *guc)
1313
{
14-
struct intel_gt *gt = guc_to_gt(guc);
15-
16-
/*
17-
* Wa_14017073508: mtl
18-
* Do not enable gucrc to avoid additional interrupts which
19-
* may disrupt pcode wa.
20-
*/
21-
if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
22-
gt->type == GT_MEDIA)
23-
return false;
24-
2514
/* GuC RC is unavailable for pre-Gen12 */
2615
return guc->submission_supported &&
27-
GRAPHICS_VER(gt->i915) >= 12;
16+
GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
2817
}
2918

3019
static bool __guc_rc_selected(struct intel_guc *guc)

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