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Merge tag 'amd-drm-fixes-5.7-2020-04-29' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.7-2020-04-29: amdgpu: - Fix a green screen on resume issue - PM fixes for SR-IOV - SDMA fix for navi - Renoir display fixes - Cursor and pageflip stuttering fixes - Misc additional display fixes UAPI: - Add additional DCC tiling flags for navi1x Used by: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents a979bb7 + b2a7b0c commit e3dcd86

24 files changed

+215
-105
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,9 +85,10 @@
8585
* - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
8686
* - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
8787
* - 3.36.0 - Allow reading more status registers on si/cik
88+
* - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
8889
*/
8990
#define KMS_DRIVER_MAJOR 3
90-
#define KMS_DRIVER_MINOR 36
91+
#define KMS_DRIVER_MINOR 37
9192
#define KMS_DRIVER_PATCHLEVEL 0
9293

9394
int amdgpu_vram_limit = 0;

‎drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,22 @@
7373
#define SDMA_OP_AQL_COPY 0
7474
#define SDMA_OP_AQL_BARRIER_OR 0
7575

76+
#define SDMA_GCR_RANGE_IS_PA (1 << 18)
77+
#define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
78+
#define SDMA_GCR_GL2_WB (1 << 15)
79+
#define SDMA_GCR_GL2_INV (1 << 14)
80+
#define SDMA_GCR_GL2_DISCARD (1 << 13)
81+
#define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
82+
#define SDMA_GCR_GL2_US (1 << 10)
83+
#define SDMA_GCR_GL1_INV (1 << 9)
84+
#define SDMA_GCR_GLV_INV (1 << 8)
85+
#define SDMA_GCR_GLK_INV (1 << 7)
86+
#define SDMA_GCR_GLK_WB (1 << 6)
87+
#define SDMA_GCR_GLM_INV (1 << 5)
88+
#define SDMA_GCR_GLM_WB (1 << 4)
89+
#define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
90+
#define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0)
91+
7692
/*define for op field*/
7793
#define SDMA_PKT_HEADER_op_offset 0
7894
#define SDMA_PKT_HEADER_op_mask 0x000000FF

‎drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -382,6 +382,18 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
382382
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
383383
uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
384384

385+
/* Invalidate L2, because if we don't do it, we might get stale cache
386+
* lines from previous IBs.
387+
*/
388+
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
389+
amdgpu_ring_write(ring, 0);
390+
amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
391+
SDMA_GCR_GL2_WB |
392+
SDMA_GCR_GLM_INV |
393+
SDMA_GCR_GLM_WB) << 16);
394+
amdgpu_ring_write(ring, 0xffffff80);
395+
amdgpu_ring_write(ring, 0xffff);
396+
385397
/* An IB packet must end on a 8 DW boundary--the next dword
386398
* must be on a 8-dword boundary. Our IB packet below is 6
387399
* dwords long, thus add x number of NOPs, such that, in
@@ -1595,7 +1607,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
15951607
SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
15961608
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
15971609
10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1598-
.emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */
1610+
.emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
15991611
.emit_ib = sdma_v5_0_ring_emit_ib,
16001612
.emit_fence = sdma_v5_0_ring_emit_fence,
16011613
.emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3340,7 +3340,8 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
33403340
const union dc_tiling_info *tiling_info,
33413341
const uint64_t info,
33423342
struct dc_plane_dcc_param *dcc,
3343-
struct dc_plane_address *address)
3343+
struct dc_plane_address *address,
3344+
bool force_disable_dcc)
33443345
{
33453346
struct dc *dc = adev->dm.dc;
33463347
struct dc_dcc_surface_param input;
@@ -3352,6 +3353,9 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
33523353
memset(&input, 0, sizeof(input));
33533354
memset(&output, 0, sizeof(output));
33543355

3356+
if (force_disable_dcc)
3357+
return 0;
3358+
33553359
if (!offset)
33563360
return 0;
33573361

@@ -3401,7 +3405,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
34013405
union dc_tiling_info *tiling_info,
34023406
struct plane_size *plane_size,
34033407
struct dc_plane_dcc_param *dcc,
3404-
struct dc_plane_address *address)
3408+
struct dc_plane_address *address,
3409+
bool force_disable_dcc)
34053410
{
34063411
const struct drm_framebuffer *fb = &afb->base;
34073412
int ret;
@@ -3507,7 +3512,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
35073512

35083513
ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
35093514
plane_size, tiling_info,
3510-
tiling_flags, dcc, address);
3515+
tiling_flags, dcc, address,
3516+
force_disable_dcc);
35113517
if (ret)
35123518
return ret;
35133519
}
@@ -3599,7 +3605,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
35993605
const struct drm_plane_state *plane_state,
36003606
const uint64_t tiling_flags,
36013607
struct dc_plane_info *plane_info,
3602-
struct dc_plane_address *address)
3608+
struct dc_plane_address *address,
3609+
bool force_disable_dcc)
36033610
{
36043611
const struct drm_framebuffer *fb = plane_state->fb;
36053612
const struct amdgpu_framebuffer *afb =
@@ -3681,7 +3688,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
36813688
plane_info->rotation, tiling_flags,
36823689
&plane_info->tiling_info,
36833690
&plane_info->plane_size,
3684-
&plane_info->dcc, address);
3691+
&plane_info->dcc, address,
3692+
force_disable_dcc);
36853693
if (ret)
36863694
return ret;
36873695

@@ -3704,6 +3712,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
37043712
struct dc_plane_info plane_info;
37053713
uint64_t tiling_flags;
37063714
int ret;
3715+
bool force_disable_dcc = false;
37073716

37083717
ret = fill_dc_scaling_info(plane_state, &scaling_info);
37093718
if (ret)
@@ -3718,9 +3727,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
37183727
if (ret)
37193728
return ret;
37203729

3730+
force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
37213731
ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
37223732
&plane_info,
3723-
&dc_plane_state->address);
3733+
&dc_plane_state->address,
3734+
force_disable_dcc);
37243735
if (ret)
37253736
return ret;
37263737

@@ -5342,6 +5353,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
53425353
uint64_t tiling_flags;
53435354
uint32_t domain;
53445355
int r;
5356+
bool force_disable_dcc = false;
53455357

53465358
dm_plane_state_old = to_dm_plane_state(plane->state);
53475359
dm_plane_state_new = to_dm_plane_state(new_state);
@@ -5400,11 +5412,13 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
54005412
dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
54015413
struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
54025414

5415+
force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
54035416
fill_plane_buffer_attributes(
54045417
adev, afb, plane_state->format, plane_state->rotation,
54055418
tiling_flags, &plane_state->tiling_info,
54065419
&plane_state->plane_size, &plane_state->dcc,
5407-
&plane_state->address);
5420+
&plane_state->address,
5421+
force_disable_dcc);
54085422
}
54095423

54105424
return 0;
@@ -6676,7 +6690,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
66766690
fill_dc_plane_info_and_addr(
66776691
dm->adev, new_plane_state, tiling_flags,
66786692
&bundle->plane_infos[planes_count],
6679-
&bundle->flip_addrs[planes_count].address);
6693+
&bundle->flip_addrs[planes_count].address,
6694+
false);
6695+
6696+
DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
6697+
new_plane_state->plane->index,
6698+
bundle->plane_infos[planes_count].dcc.enable);
66806699

66816700
bundle->surface_updates[planes_count].plane_info =
66826701
&bundle->plane_infos[planes_count];
@@ -8096,7 +8115,8 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
80968115
ret = fill_dc_plane_info_and_addr(
80978116
dm->adev, new_plane_state, tiling_flags,
80988117
plane_info,
8099-
&flip_addr->address);
8118+
&flip_addr->address,
8119+
false);
81008120
if (ret)
81018121
goto cleanup;
81028122

‎drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2908,6 +2908,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
29082908
sizeof(hpd_irq_dpcd_data),
29092909
"Status: ");
29102910

2911+
for (i = 0; i < MAX_PIPES; i++) {
2912+
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2913+
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2914+
link->dc->hwss.blank_stream(pipe_ctx);
2915+
}
2916+
29112917
for (i = 0; i < MAX_PIPES; i++) {
29122918
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
29132919
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
@@ -2927,6 +2933,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
29272933
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
29282934
dc_link_reallocate_mst_payload(link);
29292935

2936+
for (i = 0; i < MAX_PIPES; i++) {
2937+
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2938+
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2939+
link->dc->hwss.unblank_stream(pipe_ctx, &previous_link_settings);
2940+
}
2941+
29302942
status = false;
29312943
if (out_link_loss)
29322944
*out_link_loss = true;
@@ -4227,6 +4239,21 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
42274239
void dpcd_set_source_specific_data(struct dc_link *link)
42284240
{
42294241
const uint32_t post_oui_delay = 30; // 30ms
4242+
uint8_t dspc = 0;
4243+
enum dc_status ret = DC_ERROR_UNEXPECTED;
4244+
4245+
ret = core_link_read_dpcd(link, DP_DOWN_STREAM_PORT_COUNT, &dspc,
4246+
sizeof(dspc));
4247+
4248+
if (ret != DC_OK) {
4249+
DC_LOG_ERROR("Error in DP aux read transaction,"
4250+
" not writing source specific data\n");
4251+
return;
4252+
}
4253+
4254+
/* Return if OUI unsupported */
4255+
if (!(dspc & DP_OUI_SUPPORT))
4256+
return;
42304257

42314258
if (!link->dc->vendor_signature.is_valid) {
42324259
struct dpcd_amd_signature amd_signature;

‎drivers/gpu/drm/amd/display/dc/core/dc_stream.c

Lines changed: 4 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -231,34 +231,6 @@ struct dc_stream_status *dc_stream_get_status(
231231
return dc_stream_get_status_from_state(dc->current_state, stream);
232232
}
233233

234-
static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
235-
{
236-
#if defined(CONFIG_DRM_AMD_DC_DCN)
237-
unsigned int vupdate_line;
238-
unsigned int lines_to_vupdate, us_to_vupdate, vpos, nvpos;
239-
struct dc_stream_state *stream = pipe_ctx->stream;
240-
unsigned int us_per_line;
241-
242-
if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
243-
ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
244-
245-
vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
246-
if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
247-
return;
248-
249-
if (vpos >= vupdate_line)
250-
return;
251-
252-
us_per_line = stream->timing.h_total * 10000 / stream->timing.pix_clk_100hz;
253-
lines_to_vupdate = vupdate_line - vpos;
254-
us_to_vupdate = lines_to_vupdate * us_per_line;
255-
256-
/* 70 us is a conservative estimate of cursor update time*/
257-
if (us_to_vupdate < 70)
258-
udelay(us_to_vupdate);
259-
}
260-
#endif
261-
}
262234

263235
/**
264236
* dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
@@ -298,9 +270,7 @@ bool dc_stream_set_cursor_attributes(
298270

299271
if (!pipe_to_program) {
300272
pipe_to_program = pipe_ctx;
301-
302-
delay_cursor_until_vupdate(pipe_ctx, dc);
303-
dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
273+
dc->hwss.cursor_lock(dc, pipe_to_program, true);
304274
}
305275

306276
dc->hwss.set_cursor_attribute(pipe_ctx);
@@ -309,7 +279,7 @@ bool dc_stream_set_cursor_attributes(
309279
}
310280

311281
if (pipe_to_program)
312-
dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
282+
dc->hwss.cursor_lock(dc, pipe_to_program, false);
313283

314284
return true;
315285
}
@@ -349,16 +319,14 @@ bool dc_stream_set_cursor_position(
349319

350320
if (!pipe_to_program) {
351321
pipe_to_program = pipe_ctx;
352-
353-
delay_cursor_until_vupdate(pipe_ctx, dc);
354-
dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
322+
dc->hwss.cursor_lock(dc, pipe_to_program, true);
355323
}
356324

357325
dc->hwss.set_cursor_position(pipe_ctx);
358326
}
359327

360328
if (pipe_to_program)
361-
dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
329+
dc->hwss.cursor_lock(dc, pipe_to_program, false);
362330

363331
return true;
364332
}

‎drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2757,6 +2757,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
27572757
.disable_plane = dce110_power_down_fe,
27582758
.pipe_control_lock = dce_pipe_control_lock,
27592759
.interdependent_update_lock = NULL,
2760+
.cursor_lock = dce_pipe_control_lock,
27602761
.prepare_bandwidth = dce110_prepare_bandwidth,
27612762
.optimize_bandwidth = dce110_optimize_bandwidth,
27622763
.set_drr = set_drr,

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1625,6 +1625,16 @@ void dcn10_pipe_control_lock(
16251625
hws->funcs.verify_allow_pstate_change_high(dc);
16261626
}
16271627

1628+
void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
1629+
{
1630+
/* cursor lock is per MPCC tree, so only need to lock one pipe per stream */
1631+
if (!pipe || pipe->top_pipe)
1632+
return;
1633+
1634+
dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,
1635+
pipe->stream_res.opp->inst, lock);
1636+
}
1637+
16281638
static bool wait_for_reset_trigger_to_occur(
16291639
struct dc_context *dc_ctx,
16301640
struct timing_generator *tg)

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ void dcn10_pipe_control_lock(
4949
struct dc *dc,
5050
struct pipe_ctx *pipe,
5151
bool lock);
52+
void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
5253
void dcn10_blank_pixel_data(
5354
struct dc *dc,
5455
struct pipe_ctx *pipe_ctx,

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
5050
.disable_audio_stream = dce110_disable_audio_stream,
5151
.disable_plane = dcn10_disable_plane,
5252
.pipe_control_lock = dcn10_pipe_control_lock,
53+
.cursor_lock = dcn10_cursor_lock,
5354
.interdependent_update_lock = dcn10_lock_all_pipes,
5455
.prepare_bandwidth = dcn10_prepare_bandwidth,
5556
.optimize_bandwidth = dcn10_optimize_bandwidth,

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