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airliedairlied
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Merge tag 'amd-drm-fixes-5.6-2020-02-12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.6-2020-02-12: amdgpu: - Additional OD fixes for navi - Misc display fixes - VCN 2.5 DPG fix - Prevent build errors on PowerPC on some configs - GDS EDC fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 7ebdc26 + e33a8cf commit e44c1e3

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16 files changed

+108
-66
lines changed

16 files changed

+108
-66
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ static int amdgpu_perf_event_init(struct perf_event *event)
5252
return -ENOENT;
5353

5454
/* update the hw_perf_event struct with config data */
55-
hwc->conf = event->attr.config;
55+
hwc->config = event->attr.config;
5656

5757
return 0;
5858
}
@@ -74,9 +74,9 @@ static void amdgpu_perf_start(struct perf_event *event, int flags)
7474
switch (pe->pmu_perf_type) {
7575
case PERF_TYPE_AMDGPU_DF:
7676
if (!(flags & PERF_EF_RELOAD))
77-
pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);
77+
pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 1);
7878

79-
pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 0);
79+
pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 0);
8080
break;
8181
default:
8282
break;
@@ -101,7 +101,7 @@ static void amdgpu_perf_read(struct perf_event *event)
101101

102102
switch (pe->pmu_perf_type) {
103103
case PERF_TYPE_AMDGPU_DF:
104-
pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->conf,
104+
pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->config,
105105
&count);
106106
break;
107107
default:
@@ -126,7 +126,7 @@ static void amdgpu_perf_stop(struct perf_event *event, int flags)
126126

127127
switch (pe->pmu_perf_type) {
128128
case PERF_TYPE_AMDGPU_DF:
129-
pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 0);
129+
pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 0);
130130
break;
131131
default:
132132
break;
@@ -156,7 +156,8 @@ static int amdgpu_perf_add(struct perf_event *event, int flags)
156156

157157
switch (pe->pmu_perf_type) {
158158
case PERF_TYPE_AMDGPU_DF:
159-
retval = pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);
159+
retval = pe->adev->df.funcs->pmc_start(pe->adev,
160+
hwc->config, 1);
160161
break;
161162
default:
162163
return 0;
@@ -184,7 +185,7 @@ static void amdgpu_perf_del(struct perf_event *event, int flags)
184185

185186
switch (pe->pmu_perf_type) {
186187
case PERF_TYPE_AMDGPU_DF:
187-
pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 1);
188+
pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 1);
188189
break;
189190
default:
190191
break;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,7 @@ struct amdgpu_vcn_inst {
179179
struct amdgpu_irq_src irq;
180180
struct amdgpu_vcn_reg external;
181181
struct amdgpu_bo *dpg_sram_bo;
182+
struct dpg_pause_state pause_state;
182183
void *dpg_sram_cpu_addr;
183184
uint64_t dpg_sram_gpu_addr;
184185
uint32_t *dpg_sram_curr_addr;
@@ -190,8 +191,6 @@ struct amdgpu_vcn {
190191
const struct firmware *fw; /* VCN firmware */
191192
unsigned num_enc_rings;
192193
enum amd_powergating_state cur_state;
193-
struct dpg_pause_state pause_state;
194-
195194
bool indirect_sram;
196195

197196
uint8_t num_vcn_inst;

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4374,9 +4374,17 @@ static int gfx_v9_0_ecc_late_init(void *handle)
43744374
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
43754375
int r;
43764376

4377-
r = gfx_v9_0_do_edc_gds_workarounds(adev);
4378-
if (r)
4379-
return r;
4377+
/*
4378+
* Temp workaround to fix the issue that CP firmware fails to
4379+
* update read pointer when CPDMA is writing clearing operation
4380+
* to GDS in suspend/resume sequence on several cards. So just
4381+
* limit this operation in cold boot sequence.
4382+
*/
4383+
if (!adev->in_suspend) {
4384+
r = gfx_v9_0_do_edc_gds_workarounds(adev);
4385+
if (r)
4386+
return r;
4387+
}
43804388

43814389
/* requires IBs so do in late init after IB pool is initialized */
43824390
r = gfx_v9_0_do_edc_gpr_workarounds(adev);

‎drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1207,9 +1207,10 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
12071207
struct amdgpu_ring *ring;
12081208

12091209
/* pause/unpause if state is changed */
1210-
if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
1210+
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
12111211
DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1212-
adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
1212+
adev->vcn.inst[inst_idx].pause_state.fw_based,
1213+
adev->vcn.inst[inst_idx].pause_state.jpeg,
12131214
new_state->fw_based, new_state->jpeg);
12141215

12151216
reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1258,13 +1259,14 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
12581259
reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
12591260
WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
12601261
}
1261-
adev->vcn.pause_state.fw_based = new_state->fw_based;
1262+
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
12621263
}
12631264

12641265
/* pause/unpause if state is changed */
1265-
if (adev->vcn.pause_state.jpeg != new_state->jpeg) {
1266+
if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
12661267
DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1267-
adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
1268+
adev->vcn.inst[inst_idx].pause_state.fw_based,
1269+
adev->vcn.inst[inst_idx].pause_state.jpeg,
12681270
new_state->fw_based, new_state->jpeg);
12691271

12701272
reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1318,7 +1320,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
13181320
reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
13191321
WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
13201322
}
1321-
adev->vcn.pause_state.jpeg = new_state->jpeg;
1323+
adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
13221324
}
13231325

13241326
return 0;

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,9 +1137,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
11371137
int ret_code;
11381138

11391139
/* pause/unpause if state is changed */
1140-
if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
1140+
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
11411141
DRM_DEBUG("dpg pause state changed %d -> %d",
1142-
adev->vcn.pause_state.fw_based, new_state->fw_based);
1142+
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
11431143
reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
11441144
(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
11451145

@@ -1185,7 +1185,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
11851185
reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
11861186
WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
11871187
}
1188-
adev->vcn.pause_state.fw_based = new_state->fw_based;
1188+
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
11891189
}
11901190

11911191
return 0;

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1367,9 +1367,9 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
13671367
int ret_code;
13681368

13691369
/* pause/unpause if state is changed */
1370-
if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
1370+
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
13711371
DRM_DEBUG("dpg pause state changed %d -> %d",
1372-
adev->vcn.pause_state.fw_based, new_state->fw_based);
1372+
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
13731373
reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
13741374
(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
13751375

@@ -1407,14 +1407,14 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
14071407
RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
14081408

14091409
SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS,
1410-
0x0, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1410+
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
14111411
}
14121412
} else {
14131413
/* unpause dpg, no need to wait */
14141414
reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
14151415
WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
14161416
}
1417-
adev->vcn.pause_state.fw_based = new_state->fw_based;
1417+
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
14181418
}
14191419

14201420
return 0;

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8408,7 +8408,6 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
84088408
/* Calculate number of static frames before generating interrupt to
84098409
* enter PSR.
84108410
*/
8411-
unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
84128411
// Init fail safe of 2 frames static
84138412
unsigned int num_frames_static = 2;
84148413

@@ -8423,8 +8422,10 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
84238422
* Calculate number of frames such that at least 30 ms of time has
84248423
* passed.
84258424
*/
8426-
if (vsync_rate_hz != 0)
8425+
if (vsync_rate_hz != 0) {
8426+
unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
84278427
num_frames_static = (30000 / frame_time_microsec) + 1;
8428+
}
84288429

84298430
params.triggers.cursor_update = true;
84308431
params.triggers.overlay_update = true;

‎drivers/gpu/drm/amd/display/dc/bios/command_table2.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -711,10 +711,6 @@ static void enable_disp_power_gating_dmcub(
711711
power_gating.header.sub_type = DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING;
712712
power_gating.power_gating.pwr = *pwr;
713713

714-
/* ATOM_ENABLE is old API in DMUB */
715-
if (power_gating.power_gating.pwr.enable == ATOM_ENABLE)
716-
power_gating.power_gating.pwr.enable = ATOM_INIT;
717-
718714
dc_dmub_srv_cmd_queue(dmcub, &power_gating.header);
719715
dc_dmub_srv_cmd_execute(dmcub);
720716
dc_dmub_srv_wait_idle(dmcub);

‎drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,12 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)
8787
###############################################################################
8888
CLK_MGR_DCN21 = rn_clk_mgr.o rn_clk_mgr_vbios_smu.o
8989

90+
# prevent build errors regarding soft-float vs hard-float FP ABI tags
91+
# this code is currently unused on ppc64, as it applies to Renoir APUs only
92+
ifdef CONFIG_PPC64
93+
CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
94+
endif
95+
9096
AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
9197

9298
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
117117

118118
prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
119119

120-
if (safe_to_lower || prev_dppclk_khz < dppclk_khz) {
120+
if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) || prev_dppclk_khz < dppclk_khz) {
121121
clk_mgr->dccg->funcs->update_dpp_dto(
122122
clk_mgr->dccg, dpp_inst, dppclk_khz);
123123
}

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