@@ -681,8 +681,8 @@ unsigned long native_calibrate_tsc(void)
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/*
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* Denverton SoCs don't report crystal clock, and also don't support
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- * CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal
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- * clock.
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+ * CPUID_FREQ_LEAF for the calculation below, so hardcode the 25MHz
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+ * crystal clock.
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*/
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if (crystal_khz == 0 &&
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boot_cpu_data .x86_vfm == INTEL_ATOM_GOLDMONT_D )
@@ -701,10 +701,10 @@ unsigned long native_calibrate_tsc(void)
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* clock, but we can easily calculate it to a high degree of accuracy
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* by considering the crystal ratio and the CPU speed.
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*/
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- if (crystal_khz == 0 && boot_cpu_data .cpuid_level >= 0x16 ) {
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+ if (crystal_khz == 0 && boot_cpu_data .cpuid_level >= CPUID_FREQ_LEAF ) {
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unsigned int eax_base_mhz , ebx , ecx , edx ;
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- cpuid (0x16 , & eax_base_mhz , & ebx , & ecx , & edx );
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+ cpuid (CPUID_FREQ_LEAF , & eax_base_mhz , & ebx , & ecx , & edx );
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crystal_khz = eax_base_mhz * 1000 *
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eax_denominator / ebx_numerator ;
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}
@@ -739,12 +739,12 @@ static unsigned long cpu_khz_from_cpuid(void)
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if (boot_cpu_data .x86_vendor != X86_VENDOR_INTEL )
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return 0 ;
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- if (boot_cpu_data .cpuid_level < 0x16 )
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+ if (boot_cpu_data .cpuid_level < CPUID_FREQ_LEAF )
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return 0 ;
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eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0 ;
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- cpuid (0x16 , & eax_base_mhz , & ebx_max_mhz , & ecx_bus_mhz , & edx );
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+ cpuid (CPUID_FREQ_LEAF , & eax_base_mhz , & ebx_max_mhz , & ecx_bus_mhz , & edx );
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return eax_base_mhz * 1000 ;
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}
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