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riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
Since riscv and arm architecture use different interrupt definitions, use a macro SOC_PERIPHERAL_IRQ mask this difference. Signed-off-by: Alexander Sverdlin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Inochi Amaoto <[email protected]> Signed-off-by: Chen Wang <[email protected]> Signed-off-by: Chen Wang <[email protected]>
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-23
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5 files changed

+29
-23
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‎arch/riscv/boot/dts/sophgo/cv1800b.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
* Copyright (C) 2023 Jisheng Zhang <[email protected]>
44
*/
55

6+
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
7+
68
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
79
#include "cv180x-cpus.dtsi"
810
#include "cv180x.dtsi"

‎arch/riscv/boot/dts/sophgo/cv180x.dtsi

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@
3838
reg = <0>;
3939
interrupt-controller;
4040
#interrupt-cells = <2>;
41-
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
41+
interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
4242
};
4343
};
4444

@@ -56,7 +56,7 @@
5656
reg = <0>;
5757
interrupt-controller;
5858
#interrupt-cells = <2>;
59-
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
59+
interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
6060
};
6161
};
6262

@@ -74,7 +74,7 @@
7474
reg = <0>;
7575
interrupt-controller;
7676
#interrupt-cells = <2>;
77-
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
77+
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
7878
};
7979
};
8080

@@ -92,15 +92,15 @@
9292
reg = <0>;
9393
interrupt-controller;
9494
#interrupt-cells = <2>;
95-
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
95+
interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
9696
};
9797
};
9898

9999
saradc: adc@30f0000 {
100100
compatible = "sophgo,cv1800b-saradc";
101101
reg = <0x030f0000 0x1000>;
102102
clocks = <&clk CLK_SARADC>;
103-
interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
103+
interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
104104
#address-cells = <1>;
105105
#size-cells = <0>;
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status = "disabled";
@@ -125,7 +125,7 @@
125125
#size-cells = <0>;
126126
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
127127
clock-names = "ref", "pclk";
128-
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
128+
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
129129
status = "disabled";
130130
};
131131

@@ -136,7 +136,7 @@
136136
#size-cells = <0>;
137137
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
138138
clock-names = "ref", "pclk";
139-
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
139+
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
140140
status = "disabled";
141141
};
142142

@@ -147,7 +147,7 @@
147147
#size-cells = <0>;
148148
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
149149
clock-names = "ref", "pclk";
150-
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
150+
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
151151
status = "disabled";
152152
};
153153

@@ -158,7 +158,7 @@
158158
#size-cells = <0>;
159159
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
160160
clock-names = "ref", "pclk";
161-
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
161+
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
162162
status = "disabled";
163163
};
164164

@@ -169,14 +169,14 @@
169169
#size-cells = <0>;
170170
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
171171
clock-names = "ref", "pclk";
172-
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
172+
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
173173
status = "disabled";
174174
};
175175

176176
uart0: serial@4140000 {
177177
compatible = "snps,dw-apb-uart";
178178
reg = <0x04140000 0x100>;
179-
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
179+
interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
180180
clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
181181
clock-names = "baudclk", "apb_pclk";
182182
reg-shift = <2>;
@@ -187,7 +187,7 @@
187187
uart1: serial@4150000 {
188188
compatible = "snps,dw-apb-uart";
189189
reg = <0x04150000 0x100>;
190-
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
190+
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
191191
clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
192192
clock-names = "baudclk", "apb_pclk";
193193
reg-shift = <2>;
@@ -198,7 +198,7 @@
198198
uart2: serial@4160000 {
199199
compatible = "snps,dw-apb-uart";
200200
reg = <0x04160000 0x100>;
201-
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
201+
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
202202
clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
203203
clock-names = "baudclk", "apb_pclk";
204204
reg-shift = <2>;
@@ -209,7 +209,7 @@
209209
uart3: serial@4170000 {
210210
compatible = "snps,dw-apb-uart";
211211
reg = <0x04170000 0x100>;
212-
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
212+
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
213213
clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
214214
clock-names = "baudclk", "apb_pclk";
215215
reg-shift = <2>;
@@ -224,7 +224,7 @@
224224
#size-cells = <0>;
225225
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
226226
clock-names = "ssi_clk", "pclk";
227-
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
227+
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
228228
status = "disabled";
229229
};
230230

@@ -235,7 +235,7 @@
235235
#size-cells = <0>;
236236
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
237237
clock-names = "ssi_clk", "pclk";
238-
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
238+
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
239239
status = "disabled";
240240
};
241241

@@ -246,7 +246,7 @@
246246
#size-cells = <0>;
247247
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
248248
clock-names = "ssi_clk", "pclk";
249-
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
249+
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
250250
status = "disabled";
251251
};
252252

@@ -257,14 +257,14 @@
257257
#size-cells = <0>;
258258
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
259259
clock-names = "ssi_clk", "pclk";
260-
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
260+
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
261261
status = "disabled";
262262
};
263263

264264
uart4: serial@41c0000 {
265265
compatible = "snps,dw-apb-uart";
266266
reg = <0x041c0000 0x100>;
267-
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
267+
interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
268268
clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
269269
clock-names = "baudclk", "apb_pclk";
270270
reg-shift = <2>;
@@ -275,7 +275,7 @@
275275
sdhci0: mmc@4310000 {
276276
compatible = "sophgo,cv1800b-dwcmshc";
277277
reg = <0x4310000 0x1000>;
278-
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
278+
interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
279279
clocks = <&clk CLK_AXI4_SD0>,
280280
<&clk CLK_SD0>;
281281
clock-names = "core", "bus";
@@ -285,7 +285,7 @@
285285
sdhci1: mmc@4320000 {
286286
compatible = "sophgo,cv1800b-dwcmshc";
287287
reg = <0x4320000 0x1000>;
288-
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
288+
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
289289
clocks = <&clk CLK_AXI4_SD1>,
290290
<&clk CLK_SD1>;
291291
clock-names = "core", "bus";
@@ -295,7 +295,7 @@
295295
dmac: dma-controller@4330000 {
296296
compatible = "snps,axi-dma-1.01a";
297297
reg = <0x04330000 0x1000>;
298-
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
298+
interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
299299
clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
300300
clock-names = "core-clk", "cfgr-clk";
301301
#dma-cells = <1>;

‎arch/riscv/boot/dts/sophgo/cv1812h.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
* Copyright (C) 2023 Inochi Amaoto <[email protected]>
44
*/
55

6+
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
7+
68
#include <dt-bindings/interrupt-controller/irq.h>
79
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
810
#include "cv180x-cpus.dtsi"

‎arch/riscv/boot/dts/sophgo/cv181x.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
emmc: mmc@4300000 {
1212
compatible = "sophgo,cv1800b-dwcmshc";
1313
reg = <0x4300000 0x1000>;
14-
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
14+
interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
1515
clocks = <&clk CLK_AXI4_EMMC>,
1616
<&clk CLK_EMMC>;
1717
clock-names = "core", "bus";

‎arch/riscv/boot/dts/sophgo/sg2002.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
* Copyright (C) 2024 Thomas Bonnefille <[email protected]>
44
*/
55

6+
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
7+
68
#include <dt-bindings/interrupt-controller/irq.h>
79
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
810
#include "cv180x-cpus.dtsi"

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