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perf vendor events arm64: Add FUJITSU-MONAKA PMU event
Add PMU events for FUJITSU-MONAKA. And, also updated common-and-microarch.json and recommended.json. FUJITSU-MONAKA Specification URL: https://github.com/fujitsu/FUJITSU-MONAKA Reviewed-by: James Clark <[email protected]> Signed-off-by: Akio Kakuno <[email protected]> Signed-off-by: Yoshihiro Furudera <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Ian Rogers <[email protected]> Cc: Ilkka Koskinen <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Jing Zhang <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: John Garry <[email protected]> Cc: Kan Liang <[email protected]> Cc: Leo Yan <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Mike Leach <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Will Deacon <[email protected]> Cc: Xu Yang <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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‎tools/perf/pmu-events/arch/arm64/common-and-microarch.json

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‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/core-imp-def.json

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[
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{
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"ArchStdEvent": "L1I_CACHE_PRF",
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"BriefDescription": "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch."
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}
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]

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json

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[
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{
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"EventCode": "0x0182",
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"EventName": "LD_COMP_WAIT_L1_MISS",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access."
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},
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{
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"EventCode": "0x0183",
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"EventName": "LD_COMP_WAIT_L1_MISS_EX",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access."
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},
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{
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"EventCode": "0x0184",
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"EventName": "LD_COMP_WAIT",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access."
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},
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{
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"EventCode": "0x0185",
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"EventName": "LD_COMP_WAIT_EX",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access."
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},
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{
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"EventCode": "0x0186",
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"EventName": "LD_COMP_WAIT_PFP_BUSY",
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"BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port."
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},
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{
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"EventCode": "0x0187",
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"EventName": "LD_COMP_WAIT_PFP_BUSY_EX",
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"BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation."
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},
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{
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"EventCode": "0x0188",
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"EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF",
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"BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction."
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},
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{
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"EventCode": "0x0189",
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"EventName": "EU_COMP_WAIT",
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"BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction."
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},
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{
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"EventCode": "0x018A",
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"EventName": "FL_COMP_WAIT",
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"BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction."
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},
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{
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"EventCode": "0x018B",
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"EventName": "BR_COMP_WAIT",
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"BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction."
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},
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{
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"EventCode": "0x018C",
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"EventName": "ROB_EMPTY",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty."
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},
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{
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"EventCode": "0x018D",
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"EventName": "ROB_EMPTY_STQ_BUSY",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full."
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},
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{
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"EventCode": "0x018E",
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"EventName": "WFE_WFI_CYCLE",
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"BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction."
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},
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{
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"EventCode": "0x018F",
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"EventName": "RETENTION_CYCLE",
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"BriefDescription": "This event counts every cycle that the instruction unit is halted by the RETENTION state."
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},
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{
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"EventCode": "0x0190",
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"EventName": "_0INST_COMMIT",
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"BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only."
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},
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{
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"EventCode": "0x0191",
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"EventName": "_1INST_COMMIT",
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"BriefDescription": "This event counts every cycle that one instruction is committed."
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},
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{
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"EventCode": "0x0192",
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"EventName": "_2INST_COMMIT",
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"BriefDescription": "This event counts every cycle that two instructions are committed."
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},
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{
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"EventCode": "0x0193",
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"EventName": "_3INST_COMMIT",
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"BriefDescription": "This event counts every cycle that three instructions are committed."
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},
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{
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"EventCode": "0x0194",
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"EventName": "_4INST_COMMIT",
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"BriefDescription": "This event counts every cycle that four instructions are committed."
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},
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{
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"EventCode": "0x0195",
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"EventName": "_5INST_COMMIT",
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"BriefDescription": "This event counts every cycle that five instructions are committed."
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},
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{
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"EventCode": "0x0198",
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"EventName": "UOP_ONLY_COMMIT",
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"BriefDescription": "This event counts every cycle that only any micro-operations are committed."
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},
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{
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"EventCode": "0x0199",
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"EventName": "SINGLE_MOVPRFX_COMMIT",
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"BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed."
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},
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{
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"EventCode": "0x019C",
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"EventName": "LD_COMP_WAIT_L2_MISS",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache miss."
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},
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{
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"EventCode": "0x019D",
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"EventName": "LD_COMP_WAIT_L2_MISS_EX",
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"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache miss."
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}
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]

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/energy.json

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[
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{
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"EventCode": "0x01F0",
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"EventName": "EA_CORE",
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"BriefDescription": "This event counts energy consumption of core."
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},
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{
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"EventCode": "0x03F0",
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"EventName": "EA_L3",
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"BriefDescription": "This event counts energy consumption of L3 cache."
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},
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{
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"EventCode": "0x03F1",
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"EventName": "EA_LDO_LOSS",
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"BriefDescription": "This event counts energy consumption of LDO loss."
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}
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]

‎tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json

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[
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{
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"ArchStdEvent": "EXC_TAKEN",
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"BriefDescription": "This event counts each exception taken."
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},
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{
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"ArchStdEvent": "EXC_RETURN",
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"BriefDescription": "This event counts each executed exception return instruction."
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},
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{
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"ArchStdEvent": "EXC_UNDEF",
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"BriefDescription": "This event counts only other synchronous exceptions that are taken locally."
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},
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{
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"ArchStdEvent": "EXC_SVC",
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"BriefDescription": "This event counts only Supervisor Call exceptions that are taken locally."
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},
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{
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"ArchStdEvent": "EXC_PABORT",
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"BriefDescription": "This event counts only Instruction Abort exceptions that are taken locally."
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},
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{
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"ArchStdEvent": "EXC_DABORT",
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"BriefDescription": "This event counts only Data Abort or SError interrupt exceptions that are taken locally."
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},
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{
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"ArchStdEvent": "EXC_IRQ",
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"BriefDescription": "This event counts only IRQ exceptions that are taken locally, including Virtual IRQ exceptions."
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},
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{
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"ArchStdEvent": "EXC_FIQ",
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"BriefDescription": "This event counts only FIQ exceptions that are taken locally, including Virtual FIQ exceptions."
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},
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{
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"ArchStdEvent": "EXC_SMC",
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"BriefDescription": "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception."
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},
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{
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"ArchStdEvent": "EXC_HVC",
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"BriefDescription": "This event counts for both Hypervisor Call exceptions taken locally in the hypervisor and those taken as an exception from Non-secure EL1."
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}
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]

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