Skip to content

Commit e707038

Browse files
torvaldstorvalds
committed
Merge tag 'topic/nvidia-gsp-2023-11-03' of git://anongit.freedesktop.org/drm/drm
Pull drm nouveau GSP support from Dave Airlie: "This adds the initial support for the NVIDIA GSP firmware to nouveau. This firmware is a new direction for Turing+ GPUs, and is only enabled by default on Ada generation. Other generations need to use nouveau.config=NvGspRm=1 The GSP firmware takes nearly all the GPU init and power management tasks onto a risc-v CPU on the GPU. This series is mostly the work from Ben Skeggs, and Dave added some patches to rebase it to the latest firmware release which is where we will stay for as long as possible as the firmwares have no ABI stability" * tag 'topic/nvidia-gsp-2023-11-03' of git://anongit.freedesktop.org/drm/drm: (49 commits) nouveau/gsp: add some basic registry entries. nouveau/gsp: fix message signature. nouveau/gsp: move to 535.113.01 nouveau/disp: fix post-gsp build on 32-bit arm. nouveau: fix r535 build on 32-bit arm. drm/nouveau/ofa/r535: initial support drm/nouveau/nvjpg/r535: initial support drm/nouveau/nvenc/r535: initial support drm/nouveau/nvdec/r535: initial support drm/nouveau/gr/r535: initial support drm/nouveau/ce/r535: initial support drm/nouveau/fifo/r535: initial support drm/nouveau/disp/r535: initial support drm/nouveau/mmu/r535: initial support drm/nouveau/gsp/r535: add interrupt handling drm/nouveau/gsp/r535: add support for rm alloc drm/nouveau/gsp/r535: add support for rm control drm/nouveau/gsp/r535: add support for booting GSP-RM drm/nouveau/nvkm: support loading fws into sg_table drm/nouveau/kms/tu102-: disable vbios parsing when running on RM ...
2 parents aea6bf9 + 8d55b0a commit e707038

File tree

230 files changed

+14050
-140
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

230 files changed

+14050
-140
lines changed

‎drivers/gpu/drm/nouveau/dispnv50/core.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore)
4242
int version;
4343
int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
4444
} cores[] = {
45+
{ AD102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
4546
{ GA102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
4647
{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
4748
{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },

‎drivers/gpu/drm/nouveau/dispnv50/disp.c

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1592,6 +1592,148 @@ nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *st
15921592
nv_encoder->crtc = NULL;
15931593
}
15941594

1595+
// common/inc/displayport/displayport.h
1596+
#define DP_CONFIG_WATERMARK_ADJUST 2
1597+
#define DP_CONFIG_WATERMARK_LIMIT 20
1598+
#define DP_CONFIG_INCREASED_WATERMARK_ADJUST 8
1599+
#define DP_CONFIG_INCREASED_WATERMARK_LIMIT 22
1600+
1601+
static bool
1602+
nv50_sor_dp_watermark_sst(struct nouveau_encoder *outp,
1603+
struct nv50_head *head, struct nv50_head_atom *asyh)
1604+
{
1605+
bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP;
1606+
u64 minRate = outp->dp.link_bw * 1000;
1607+
unsigned tuSize = 64;
1608+
unsigned waterMark;
1609+
unsigned hBlankSym;
1610+
unsigned vBlankSym;
1611+
unsigned watermarkAdjust = DP_CONFIG_WATERMARK_ADJUST;
1612+
unsigned watermarkMinimum = DP_CONFIG_WATERMARK_LIMIT;
1613+
// depth is multiplied by 16 in case of DSC enable
1614+
s32 hblank_symbols;
1615+
// number of link clocks per line.
1616+
int vblank_symbols = 0;
1617+
bool bEnableDsc = false;
1618+
unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke;
1619+
unsigned rasterWidth = asyh->mode.h.active;
1620+
unsigned depth = asyh->or.bpc * 3;
1621+
unsigned DSC_FACTOR = bEnableDsc ? 16 : 1;
1622+
u64 pixelClockHz = asyh->mode.clock * 1000;
1623+
u64 PrecisionFactor = 100000, ratioF, watermarkF;
1624+
u32 numLanesPerLink = outp->dp.link_nr;
1625+
u32 numSymbolsPerLine;
1626+
u32 BlankingBits;
1627+
u32 surfaceWidthPerLink;
1628+
u32 PixelSteeringBits;
1629+
u64 NumBlankingLinkClocks;
1630+
u32 MinHBlank;
1631+
1632+
if (outp->outp.info.dp.increased_wm) {
1633+
watermarkAdjust = DP_CONFIG_INCREASED_WATERMARK_ADJUST;
1634+
watermarkMinimum = DP_CONFIG_INCREASED_WATERMARK_LIMIT;
1635+
}
1636+
1637+
if ((pixelClockHz * depth) >= (8 * minRate * outp->dp.link_nr * DSC_FACTOR))
1638+
{
1639+
return false;
1640+
}
1641+
1642+
//
1643+
// For DSC, if (pclk * bpp) < (1/64 * orclk * 8 * lanes) then some TU may end up with
1644+
// 0 active symbols. This may cause HW hang. Bug 200379426
1645+
//
1646+
if ((bEnableDsc) &&
1647+
((pixelClockHz * depth) < div_u64(8 * minRate * outp->dp.link_nr * DSC_FACTOR, 64)))
1648+
{
1649+
return false;
1650+
}
1651+
1652+
//
1653+
// Perform the SST calculation.
1654+
// For auto mode the watermark calculation does not need to track accumulated error the
1655+
// formulas for manual mode will not work. So below calculation was extracted from the DTB.
1656+
//
1657+
ratioF = div_u64((u64)pixelClockHz * depth * PrecisionFactor, DSC_FACTOR);
1658+
1659+
ratioF = div_u64(ratioF, 8 * (u64) minRate * outp->dp.link_nr);
1660+
1661+
if (PrecisionFactor < ratioF) // Assert if we will end up with a negative number in below
1662+
return false;
1663+
1664+
watermarkF = div_u64(ratioF * tuSize * (PrecisionFactor - ratioF), PrecisionFactor);
1665+
waterMark = (unsigned)(watermarkAdjust + (div_u64(2 * div_u64(depth * PrecisionFactor, 8 * numLanesPerLink * DSC_FACTOR) + watermarkF, PrecisionFactor)));
1666+
1667+
//
1668+
// Bounds check the watermark
1669+
//
1670+
numSymbolsPerLine = div_u64(surfaceWidth * depth, 8 * outp->dp.link_nr * DSC_FACTOR);
1671+
1672+
if (WARN_ON(waterMark > 39 || waterMark > numSymbolsPerLine))
1673+
return false;
1674+
1675+
//
1676+
// Clamp the low side
1677+
//
1678+
if (waterMark < watermarkMinimum)
1679+
waterMark = watermarkMinimum;
1680+
1681+
//Bits to send BS/BE/Extra symbols due to pixel padding
1682+
//Also accounts for enhanced framing.
1683+
BlankingBits = 3*8*numLanesPerLink + (enhancedFraming ? 3*8*numLanesPerLink : 0);
1684+
1685+
//VBID/MVID/MAUD sent 4 times all the time
1686+
BlankingBits += 3*8*4;
1687+
1688+
surfaceWidthPerLink = surfaceWidth;
1689+
1690+
//Extra bits sent due to pixel steering
1691+
u32 remain;
1692+
div_u64_rem(surfaceWidthPerLink, numLanesPerLink, &remain);
1693+
PixelSteeringBits = remain ? div_u64((numLanesPerLink - remain) * depth, DSC_FACTOR) : 0;
1694+
1695+
BlankingBits += PixelSteeringBits;
1696+
NumBlankingLinkClocks = div_u64((u64)BlankingBits * PrecisionFactor, (8 * numLanesPerLink));
1697+
MinHBlank = (u32)(div_u64(div_u64(NumBlankingLinkClocks * pixelClockHz, minRate), PrecisionFactor));
1698+
MinHBlank += 12;
1699+
1700+
if (WARN_ON(MinHBlank > rasterWidth - surfaceWidth))
1701+
return false;
1702+
1703+
// Bug 702290 - Active Width should be greater than 60
1704+
if (WARN_ON(surfaceWidth <= 60))
1705+
return false;
1706+
1707+
1708+
hblank_symbols = (s32)(div_u64((u64)(rasterWidth - surfaceWidth - MinHBlank) * minRate, pixelClockHz));
1709+
1710+
//reduce HBlank Symbols to account for secondary data packet
1711+
hblank_symbols -= 1; //Stuffer latency to send BS
1712+
hblank_symbols -= 3; //SPKT latency to send data to stuffer
1713+
1714+
hblank_symbols -= numLanesPerLink == 1 ? 9 : numLanesPerLink == 2 ? 6 : 3;
1715+
1716+
hBlankSym = (hblank_symbols < 0) ? 0 : hblank_symbols;
1717+
1718+
// Refer to dev_disp.ref for more information.
1719+
// # symbols/vblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - SetRasterBlankStart.X - 40) * link_clk / pclk) - Y - 1;
1720+
// where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39
1721+
if (surfaceWidth < 40)
1722+
{
1723+
vblank_symbols = 0;
1724+
}
1725+
else
1726+
{
1727+
vblank_symbols = (s32)((div_u64((u64)(surfaceWidth - 40) * minRate, pixelClockHz))) - 1;
1728+
1729+
vblank_symbols -= numLanesPerLink == 1 ? 39 : numLanesPerLink == 2 ? 21 : 12;
1730+
}
1731+
1732+
vBlankSym = (vblank_symbols < 0) ? 0 : vblank_symbols;
1733+
1734+
return nvif_outp_dp_sst(&outp->outp, head->base.index, waterMark, hBlankSym, vBlankSym);
1735+
}
1736+
15951737
static void
15961738
nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
15971739
{
@@ -1679,6 +1821,7 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
16791821
break;
16801822
case DCB_OUTPUT_DP:
16811823
nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc);
1824+
nv50_sor_dp_watermark_sst(nv_encoder, head, asyh);
16821825
depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
16831826

16841827
if (nv_encoder->outp.or.link & 1)

‎drivers/gpu/drm/nouveau/include/nvif/cl0080.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ struct nv_device_info_v0 {
3535
#define NV_DEVICE_INFO_V0_VOLTA 0x0b
3636
#define NV_DEVICE_INFO_V0_TURING 0x0c
3737
#define NV_DEVICE_INFO_V0_AMPERE 0x0d
38+
#define NV_DEVICE_INFO_V0_ADA 0x0e
3839
__u8 family;
3940
__u8 pad06[2];
4041
__u64 ram_size;
@@ -90,6 +91,8 @@ struct nv_device_time_v0 {
9091
#define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000
9192
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000
9293
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000
94+
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVJPG 0x00020000
95+
#define NV_DEVICE_HOST_RUNLIST_ENGINES_OFA 0x00040000
9396
/* Returns the number of available channels on runlist(data). */
9497
#define NV_DEVICE_HOST_RUNLIST_CHANNELS NV_DEVICE_HOST(0x00000101)
9598
#endif

‎drivers/gpu/drm/nouveau/include/nvif/class.h

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,7 @@
104104
#define GV100_DISP /* if0010.h */ 0x0000c370
105105
#define TU102_DISP /* if0010.h */ 0x0000c570
106106
#define GA102_DISP /* if0010.h */ 0x0000c670
107+
#define AD102_DISP /* if0010.h */ 0x0000c770
107108

108109
#define GV100_DISP_CAPS 0x0000c373
109110

@@ -154,6 +155,7 @@
154155
#define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d
155156
#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
156157
#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
158+
#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
157159

158160
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
159161
#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
@@ -192,8 +194,15 @@
192194

193195
#define AMPERE_B /* cl9097.h */ 0x0000c797
194196

197+
#define ADA_A /* cl9097.h */ 0x0000c997
198+
195199
#define NV74_BSP 0x000074b0
196200

201+
#define NVC4B0_VIDEO_DECODER 0x0000c4b0
202+
#define NVC6B0_VIDEO_DECODER 0x0000c6b0
203+
#define NVC7B0_VIDEO_DECODER 0x0000c7b0
204+
#define NVC9B0_VIDEO_DECODER 0x0000c9b0
205+
197206
#define GT212_MSVLD 0x000085b1
198207
#define IGT21A_MSVLD 0x000086b1
199208
#define G98_MSVLD 0x000088b1
@@ -222,6 +231,10 @@
222231
#define AMPERE_DMA_COPY_A 0x0000c6b5
223232
#define AMPERE_DMA_COPY_B 0x0000c7b5
224233

234+
#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
235+
#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
236+
#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
237+
225238
#define FERMI_DECOMPRESS 0x000090b8
226239

227240
#define NV50_COMPUTE 0x000050c0
@@ -237,6 +250,14 @@
237250
#define VOLTA_COMPUTE_A 0x0000c3c0
238251
#define TURING_COMPUTE_A 0x0000c5c0
239252
#define AMPERE_COMPUTE_B 0x0000c7c0
253+
#define ADA_COMPUTE_A 0x0000c9c0
240254

241255
#define NV74_CIPHER 0x000074c1
256+
257+
#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
258+
#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
259+
260+
#define NVC6FA_VIDEO_OFA 0x0000c6fa
261+
#define NVC7FA_VIDEO_OFA 0x0000c7fa
262+
#define NVC9FA_VIDEO_OFA 0x0000c9fa
242263
#endif

‎drivers/gpu/drm/nouveau/include/nvkm/core/device.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ struct nvkm_device {
4646
GV100 = 0x140,
4747
TU100 = 0x160,
4848
GA100 = 0x170,
49+
AD100 = 0x190,
4950
} card_type;
5051
u32 chipset;
5152
u8 chiprev;

‎drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ int nvkm_falcon_pio_rd(struct nvkm_falcon *, u8 port, enum nvkm_falcon_mem type,
4848
const u8 *img, u32 img_base, int len);
4949
int nvkm_falcon_dma_wr(struct nvkm_falcon *, const u8 *img, u64 dma_addr, u32 dma_base,
5050
enum nvkm_falcon_mem mem_type, u32 mem_base, int len, bool sec);
51+
bool nvkm_falcon_riscv_active(struct nvkm_falcon *);
52+
void nvkm_falcon_intr_retrigger(struct nvkm_falcon *);
5153

5254
int gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);
5355
int gm200_flcn_disable(struct nvkm_falcon *);
@@ -61,10 +63,15 @@ void gm200_flcn_tracepc(struct nvkm_falcon *);
6163
int gp102_flcn_reset_eng(struct nvkm_falcon *);
6264
extern const struct nvkm_falcon_func_pio gp102_flcn_emem_pio;
6365

66+
bool tu102_flcn_riscv_active(struct nvkm_falcon *);
67+
68+
void ga100_flcn_intr_retrigger(struct nvkm_falcon *);
69+
6470
int ga102_flcn_select(struct nvkm_falcon *);
6571
int ga102_flcn_reset_prep(struct nvkm_falcon *);
6672
int ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);
6773
extern const struct nvkm_falcon_func_dma ga102_flcn_dma;
74+
bool ga102_flcn_riscv_active(struct nvkm_falcon *);
6875

6976
void nvkm_falcon_v1_load_imem(struct nvkm_falcon *,
7077
void *, u32, u32, u16, u8, bool);

‎drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ struct nvkm_firmware {
1010
enum nvkm_firmware_type {
1111
NVKM_FIRMWARE_IMG_RAM,
1212
NVKM_FIRMWARE_IMG_DMA,
13+
NVKM_FIRMWARE_IMG_SGT,
1314
} type;
1415
} *func;
1516
const char *name;
@@ -21,7 +22,10 @@ struct nvkm_firmware {
2122

2223
struct nvkm_firmware_mem {
2324
struct nvkm_memory memory;
24-
struct scatterlist sgl;
25+
union {
26+
struct scatterlist sgl; /* DMA */
27+
struct sg_table sgt; /* SGT */
28+
};
2529
} mem;
2630
};
2731

‎drivers/gpu/drm/nouveau/include/nvkm/core/layout.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: MIT */
2-
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_TOP , struct nvkm_top , top)
32
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_GSP , struct nvkm_gsp , gsp)
3+
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_TOP , struct nvkm_top , top)
44
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_VFN , struct nvkm_vfn , vfn)
55
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_PCI , struct nvkm_pci , pci)
66
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_VBIOS , struct nvkm_bios , bios)
@@ -42,9 +42,9 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSENC , struct nvkm_engine , msenc)
4242
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC , struct nvkm_engine , mspdec)
4343
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP , struct nvkm_engine , msppp)
4444
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSVLD , struct nvkm_engine , msvld)
45-
NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 5)
45+
NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 8)
4646
NVKM_LAYOUT_INST(NVKM_ENGINE_NVENC , struct nvkm_nvenc , nvenc, 3)
47-
NVKM_LAYOUT_ONCE(NVKM_ENGINE_NVJPG , struct nvkm_engine , nvjpg)
47+
NVKM_LAYOUT_INST(NVKM_ENGINE_NVJPG , struct nvkm_engine , nvjpg, 8)
4848
NVKM_LAYOUT_ONCE(NVKM_ENGINE_OFA , struct nvkm_engine , ofa)
4949
NVKM_LAYOUT_ONCE(NVKM_ENGINE_PM , struct nvkm_pm , pm)
5050
NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC , struct nvkm_engine , sec)

‎drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,29 @@
55
#include <core/engine.h>
66
#include <core/object.h>
77
#include <core/event.h>
8+
#include <subdev/gsp.h>
89

910
struct nvkm_disp {
1011
const struct nvkm_disp_func *func;
1112
struct nvkm_engine engine;
1213

14+
struct {
15+
struct nvkm_gsp_client client;
16+
struct nvkm_gsp_device device;
17+
18+
struct nvkm_gsp_object objcom;
19+
struct nvkm_gsp_object object;
20+
21+
#define NVKM_DPYID_PLUG BIT(0)
22+
#define NVKM_DPYID_UNPLUG BIT(1)
23+
#define NVKM_DPYID_IRQ BIT(2)
24+
struct nvkm_event event;
25+
struct nvkm_gsp_event hpd;
26+
struct nvkm_gsp_event irq;
27+
28+
u32 assigned_sors;
29+
} rm;
30+
1331
struct list_head heads;
1432
struct list_head iors;
1533
struct list_head outps;
@@ -69,4 +87,5 @@ int gp102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
6987
int gv100_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
7088
int tu102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
7189
int ga102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
90+
int ad102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
7291
#endif

‎drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@ struct nvkm_falcon_func {
6262
int (*enable)(struct nvkm_falcon *);
6363
int (*select)(struct nvkm_falcon *);
6464
u32 addr2;
65+
u32 riscv_irqmask;
6566
bool reset_pmc;
6667
int (*reset_eng)(struct nvkm_falcon *);
6768
int (*reset_prep)(struct nvkm_falcon *);
@@ -87,6 +88,9 @@ struct nvkm_falcon_func {
8788
u32 stride;
8889
} cmdq, msgq;
8990

91+
bool (*riscv_active)(struct nvkm_falcon *);
92+
void (*intr_retrigger)(struct nvkm_falcon *);
93+
9094
struct {
9195
u32 *data;
9296
u32 size;

0 commit comments

Comments
 (0)