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Merge tag 'renesas-clk-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel Selector (ISPCS), and video capture (VIN) clocks on R-Car V4H - Add video capture (VIN) clocks on R-Car V3H - Add Cortex-A53 System CPU (Z2) clocks on R-Car V3M and V3H - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Convert to platform remove callback returning void clk: renesas: r9a06g032: Improve clock tables clk: renesas: r9a06g032: Document structs clk: renesas: r9a06g032: Drop unused fields clk: renesas: r9a06g032: Improve readability clk: renesas: r8a77980: Add Z2 clock clk: renesas: r8a77970: Add Z2 clock clk: renesas: r8a77995: Fix VIN parent clock clk: renesas: r8a77980: Add VIN clocks clk: renesas: r8a779g0: Add VIN clocks clk: renesas: r8a779g0: Add ISPCS clocks clk: renesas: r8a779g0: Add CSI-2 clocks clk: renesas: r8a779g0: Add thermal clock clk: renesas: r8a779g0: Add Audio clocks clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
2 parents fe15c26 + 72cd843 commit e724167

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7 files changed

+590
-204
lines changed

7 files changed

+590
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lines changed

‎drivers/clk/renesas/r8a77970-cpg-mssr.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
7676
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
7777

7878
/* Core Clock Outputs */
79+
DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1),
7980
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8081
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8182
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),

‎drivers/clk/renesas/r8a77980-cpg-mssr.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
7272
DEF_RATE(".oco", CLK_OCO, 32768),
7373

7474
/* Core Clock Outputs */
75+
DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1),
7576
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
7677
DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
7778
DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -150,11 +151,27 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
150151
DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
151152
DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
152153
DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
154+
DEF_MOD("vin15", 604, R8A77980_CLK_S2D1),
155+
DEF_MOD("vin14", 605, R8A77980_CLK_S2D1),
156+
DEF_MOD("vin13", 608, R8A77980_CLK_S2D1),
157+
DEF_MOD("vin12", 612, R8A77980_CLK_S2D1),
158+
DEF_MOD("vin11", 618, R8A77980_CLK_S2D1),
153159
DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
160+
DEF_MOD("vin10", 625, R8A77980_CLK_S2D1),
161+
DEF_MOD("vin9", 627, R8A77980_CLK_S2D1),
162+
DEF_MOD("vin8", 628, R8A77980_CLK_S2D1),
154163
DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
155164
DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
156165
DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
157166
DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
167+
DEF_MOD("vin7", 804, R8A77980_CLK_S2D1),
168+
DEF_MOD("vin6", 805, R8A77980_CLK_S2D1),
169+
DEF_MOD("vin5", 806, R8A77980_CLK_S2D1),
170+
DEF_MOD("vin4", 807, R8A77980_CLK_S2D1),
171+
DEF_MOD("vin3", 808, R8A77980_CLK_S2D1),
172+
DEF_MOD("vin2", 809, R8A77980_CLK_S2D1),
173+
DEF_MOD("vin1", 810, R8A77980_CLK_S2D1),
174+
DEF_MOD("vin0", 811, R8A77980_CLK_S2D1),
158175
DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
159176
DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
160177
DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),

‎drivers/clk/renesas/r8a77995-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
167167
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
168168
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
169169
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
170-
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
170+
DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
171171
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
172172
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
173173
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),

‎drivers/clk/renesas/r8a779g0-cpg-mssr.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
146146
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
147147
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
148148
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
149+
DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
149150
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
150151
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
151152

@@ -165,6 +166,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
165166
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
166167
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
167168
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
169+
DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
170+
DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
168171
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
169172
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
170173
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
@@ -181,6 +184,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
181184
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
182185
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
183186
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
187+
DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO),
188+
DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO),
184189
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
185190
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
186191
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
@@ -202,6 +207,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
202207
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
203208
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
204209
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
210+
DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO),
211+
DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO),
212+
DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO),
213+
DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO),
214+
DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO),
215+
DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO),
216+
DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO),
217+
DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO),
218+
DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO),
219+
DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO),
220+
DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO),
221+
DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO),
222+
DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO),
223+
DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO),
224+
DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO),
225+
DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO),
205226
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
206227
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
207228
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
@@ -213,6 +234,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
213234
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
214235
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
215236
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
237+
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
238+
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
239+
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
216240
};
217241

218242
/*

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