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XiaoWang1772palmer-dabbelt
XiaoWang1772
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palmer-dabbelt
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riscv: Rearrange hwcap.h and cpufeature.h
Now hwcap.h and cpufeature.h are mutually including each other, and most of the variable/API declarations in hwcap.h are implemented in cpufeature.c, so, it's better to move them into cpufeature.h and leave only macros for ISA extension logical IDs in hwcap.h. BTW, the riscv_isa_extension_mask macro is not used now, so this patch removes it. Suggested-by: Andrew Jones <[email protected]> Signed-off-by: Xiao Wang <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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14 files changed

+95
-102
lines changed

14 files changed

+95
-102
lines changed

‎arch/riscv/include/asm/cpufeature.h

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,10 @@
77
#define _ASM_CPUFEATURE_H
88

99
#include <linux/bitmap.h>
10+
#include <linux/jump_label.h>
1011
#include <asm/hwcap.h>
12+
#include <asm/alternative-macros.h>
13+
#include <asm/errno.h>
1114

1215
/*
1316
* These are probed via a device_initcall(), via either the SBI or directly
@@ -50,4 +53,84 @@ static inline bool check_unaligned_access_emulated(int cpu)
5053
static inline void unaligned_emulation_finish(void) {}
5154
#endif
5255

56+
unsigned long riscv_get_elf_hwcap(void);
57+
58+
struct riscv_isa_ext_data {
59+
const unsigned int id;
60+
const char *name;
61+
const char *property;
62+
};
63+
64+
extern const struct riscv_isa_ext_data riscv_isa_ext[];
65+
extern const size_t riscv_isa_ext_count;
66+
extern bool riscv_isa_fallback;
67+
68+
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
69+
70+
bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
71+
#define riscv_isa_extension_available(isa_bitmap, ext) \
72+
__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
73+
74+
static __always_inline bool
75+
riscv_has_extension_likely(const unsigned long ext)
76+
{
77+
compiletime_assert(ext < RISCV_ISA_EXT_MAX,
78+
"ext must be < RISCV_ISA_EXT_MAX");
79+
80+
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
81+
asm_volatile_goto(
82+
ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
83+
:
84+
: [ext] "i" (ext)
85+
:
86+
: l_no);
87+
} else {
88+
if (!__riscv_isa_extension_available(NULL, ext))
89+
goto l_no;
90+
}
91+
92+
return true;
93+
l_no:
94+
return false;
95+
}
96+
97+
static __always_inline bool
98+
riscv_has_extension_unlikely(const unsigned long ext)
99+
{
100+
compiletime_assert(ext < RISCV_ISA_EXT_MAX,
101+
"ext must be < RISCV_ISA_EXT_MAX");
102+
103+
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
104+
asm_volatile_goto(
105+
ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
106+
:
107+
: [ext] "i" (ext)
108+
:
109+
: l_yes);
110+
} else {
111+
if (__riscv_isa_extension_available(NULL, ext))
112+
goto l_yes;
113+
}
114+
115+
return false;
116+
l_yes:
117+
return true;
118+
}
119+
120+
static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
121+
{
122+
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
123+
return true;
124+
125+
return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
126+
}
127+
128+
static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
129+
{
130+
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
131+
return true;
132+
133+
return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
134+
}
135+
53136
#endif

‎arch/riscv/include/asm/elf.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
#include <asm/auxvec.h>
1515
#include <asm/byteorder.h>
1616
#include <asm/cacheinfo.h>
17-
#include <asm/hwcap.h>
17+
#include <asm/cpufeature.h>
1818

1919
/*
2020
* These are used to set parameters in the core dumps.

‎arch/riscv/include/asm/hwcap.h

Lines changed: 0 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,6 @@
88
#ifndef _ASM_RISCV_HWCAP_H
99
#define _ASM_RISCV_HWCAP_H
1010

11-
#include <asm/alternative-macros.h>
12-
#include <asm/errno.h>
13-
#include <linux/bits.h>
1411
#include <uapi/asm/hwcap.h>
1512

1613
#define RISCV_ISA_EXT_a ('a' - 'a')
@@ -67,92 +64,4 @@
6764
#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
6865
#endif
6966

70-
#ifndef __ASSEMBLY__
71-
72-
#include <linux/jump_label.h>
73-
#include <asm/cpufeature.h>
74-
75-
unsigned long riscv_get_elf_hwcap(void);
76-
77-
struct riscv_isa_ext_data {
78-
const unsigned int id;
79-
const char *name;
80-
const char *property;
81-
};
82-
83-
extern const struct riscv_isa_ext_data riscv_isa_ext[];
84-
extern const size_t riscv_isa_ext_count;
85-
extern bool riscv_isa_fallback;
86-
87-
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
88-
89-
#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
90-
91-
bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
92-
#define riscv_isa_extension_available(isa_bitmap, ext) \
93-
__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
94-
95-
static __always_inline bool
96-
riscv_has_extension_likely(const unsigned long ext)
97-
{
98-
compiletime_assert(ext < RISCV_ISA_EXT_MAX,
99-
"ext must be < RISCV_ISA_EXT_MAX");
100-
101-
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
102-
asm_volatile_goto(
103-
ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
104-
:
105-
: [ext] "i" (ext)
106-
:
107-
: l_no);
108-
} else {
109-
if (!__riscv_isa_extension_available(NULL, ext))
110-
goto l_no;
111-
}
112-
113-
return true;
114-
l_no:
115-
return false;
116-
}
117-
118-
static __always_inline bool
119-
riscv_has_extension_unlikely(const unsigned long ext)
120-
{
121-
compiletime_assert(ext < RISCV_ISA_EXT_MAX,
122-
"ext must be < RISCV_ISA_EXT_MAX");
123-
124-
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
125-
asm_volatile_goto(
126-
ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
127-
:
128-
: [ext] "i" (ext)
129-
:
130-
: l_yes);
131-
} else {
132-
if (__riscv_isa_extension_available(NULL, ext))
133-
goto l_yes;
134-
}
135-
136-
return false;
137-
l_yes:
138-
return true;
139-
}
140-
141-
static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
142-
{
143-
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
144-
return true;
145-
146-
return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
147-
}
148-
149-
static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
150-
{
151-
if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
152-
return true;
153-
154-
return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
155-
}
156-
#endif
157-
15867
#endif /* _ASM_RISCV_HWCAP_H */

‎arch/riscv/include/asm/pgtable.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -291,6 +291,7 @@ static inline pte_t pud_pte(pud_t pud)
291291
}
292292

293293
#ifdef CONFIG_RISCV_ISA_SVNAPOT
294+
#include <asm/cpufeature.h>
294295

295296
static __always_inline bool has_svnapot(void)
296297
{

‎arch/riscv/include/asm/switch_to.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
#include <linux/jump_label.h>
1010
#include <linux/sched/task_stack.h>
1111
#include <asm/vector.h>
12-
#include <asm/hwcap.h>
12+
#include <asm/cpufeature.h>
1313
#include <asm/processor.h>
1414
#include <asm/ptrace.h>
1515
#include <asm/csr.h>

‎arch/riscv/include/asm/vector.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#include <linux/sched.h>
1616
#include <linux/sched/task_stack.h>
1717
#include <asm/ptrace.h>
18-
#include <asm/hwcap.h>
18+
#include <asm/cpufeature.h>
1919
#include <asm/csr.h>
2020
#include <asm/asm.h>
2121

‎arch/riscv/kvm/aia.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
#include <linux/kvm_host.h>
1515
#include <linux/percpu.h>
1616
#include <linux/spinlock.h>
17-
#include <asm/hwcap.h>
17+
#include <asm/cpufeature.h>
1818
#include <asm/kvm_aia_imsic.h>
1919

2020
struct aia_hgei_control {

‎arch/riscv/kvm/main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include <linux/module.h>
1212
#include <linux/kvm_host.h>
1313
#include <asm/csr.h>
14-
#include <asm/hwcap.h>
14+
#include <asm/cpufeature.h>
1515
#include <asm/sbi.h>
1616

1717
long kvm_arch_dev_ioctl(struct file *filp,

‎arch/riscv/kvm/tlb.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include <linux/kvm_host.h>
1313
#include <asm/cacheflush.h>
1414
#include <asm/csr.h>
15-
#include <asm/hwcap.h>
15+
#include <asm/cpufeature.h>
1616
#include <asm/insn-def.h>
1717

1818
#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)

‎arch/riscv/kvm/vcpu_fp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include <linux/err.h>
1212
#include <linux/kvm_host.h>
1313
#include <linux/uaccess.h>
14-
#include <asm/hwcap.h>
14+
#include <asm/cpufeature.h>
1515

1616
#ifdef CONFIG_FPU
1717
void kvm_riscv_vcpu_fp_reset(struct kvm_vcpu *vcpu)

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