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mbrost05rodrigovivi
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drm/i915/guc: Support programming the EU priority in the GuC descriptor
In GuC submission mode the EU priority must be updated by the GuC rather than the driver as the GuC owns the programming of the context descriptor. Given that the GuC code uses the GuC priorities, we can't use a generic function using i915 priorities for both execlists and GuC submission. The existing function has therefore been pushed to the execlists back-end while a new one has been added for GuC. v2: correctly use the GuC prio. Cc: John Harrison <[email protected]> Cc: Matt Roper <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: John Harrison <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit a5c89f7) Signed-off-by: Rodrigo Vivi <[email protected]>
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drivers/gpu/drm/i915/gt/intel_execlists_submission.c

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -661,6 +661,16 @@ static inline void execlists_schedule_out(struct i915_request *rq)
661661
i915_request_put(rq);
662662
}
663663

664+
static u32 map_i915_prio_to_lrc_desc_prio(int prio)
665+
{
666+
if (prio > I915_PRIORITY_NORMAL)
667+
return GEN12_CTX_PRIORITY_HIGH;
668+
else if (prio < I915_PRIORITY_NORMAL)
669+
return GEN12_CTX_PRIORITY_LOW;
670+
else
671+
return GEN12_CTX_PRIORITY_NORMAL;
672+
}
673+
664674
static u64 execlists_update_context(struct i915_request *rq)
665675
{
666676
struct intel_context *ce = rq->context;
@@ -669,7 +679,7 @@ static u64 execlists_update_context(struct i915_request *rq)
669679

670680
desc = ce->lrc.desc;
671681
if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
672-
desc |= lrc_desc_priority(rq_prio(rq));
682+
desc |= map_i915_prio_to_lrc_desc_prio(rq_prio(rq));
673683

674684
/*
675685
* WaIdleLiteRestore:bdw,skl

drivers/gpu/drm/i915/gt/intel_lrc.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -111,16 +111,6 @@ enum {
111111
#define XEHP_SW_COUNTER_SHIFT 58
112112
#define XEHP_SW_COUNTER_WIDTH 6
113113

114-
static inline u32 lrc_desc_priority(int prio)
115-
{
116-
if (prio > I915_PRIORITY_NORMAL)
117-
return GEN12_CTX_PRIORITY_HIGH;
118-
else if (prio < I915_PRIORITY_NORMAL)
119-
return GEN12_CTX_PRIORITY_LOW;
120-
else
121-
return GEN12_CTX_PRIORITY_NORMAL;
122-
}
123-
124114
static inline void lrc_runtime_start(struct intel_context *ce)
125115
{
126116
struct intel_context_stats *stats = &ce->stats;

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2394,6 +2394,26 @@ static int guc_context_policy_init(struct intel_context *ce, bool loop)
23942394
return ret;
23952395
}
23962396

2397+
static u32 map_guc_prio_to_lrc_desc_prio(u8 prio)
2398+
{
2399+
/*
2400+
* this matches the mapping we do in map_i915_prio_to_guc_prio()
2401+
* (e.g. prio < I915_PRIORITY_NORMAL maps to GUC_CLIENT_PRIORITY_NORMAL)
2402+
*/
2403+
switch (prio) {
2404+
default:
2405+
MISSING_CASE(prio);
2406+
fallthrough;
2407+
case GUC_CLIENT_PRIORITY_KMD_NORMAL:
2408+
return GEN12_CTX_PRIORITY_NORMAL;
2409+
case GUC_CLIENT_PRIORITY_NORMAL:
2410+
return GEN12_CTX_PRIORITY_LOW;
2411+
case GUC_CLIENT_PRIORITY_HIGH:
2412+
case GUC_CLIENT_PRIORITY_KMD_HIGH:
2413+
return GEN12_CTX_PRIORITY_HIGH;
2414+
}
2415+
}
2416+
23972417
static void prepare_context_registration_info(struct intel_context *ce,
23982418
struct guc_ctxt_registration_info *info)
23992419
{
@@ -2420,6 +2440,8 @@ static void prepare_context_registration_info(struct intel_context *ce,
24202440
*/
24212441
info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
24222442
info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
2443+
if (engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
2444+
info->hwlrca_lo |= map_guc_prio_to_lrc_desc_prio(ce->guc_state.prio);
24232445
info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
24242446

24252447
/*

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