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Evan Quanalexdeucher
Evan Quan
authored and
alexdeucher
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drm/amd/powerplay: maximum code sharing around watermarks setting
Maximum code sharing. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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7 files changed

+166
-182
lines changed

7 files changed

+166
-182
lines changed

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 4 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1486,23 +1486,12 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
14861486
return 0;
14871487
}
14881488

1489-
mutex_lock(&smu->mutex);
1490-
1491-
/* pass data to smu controller */
1492-
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1493-
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1494-
ret = smu_write_watermarks_table(smu);
1495-
1496-
if (ret) {
1497-
mutex_unlock(&smu->mutex);
1498-
DRM_ERROR("Failed to update WMTABLE!\n");
1499-
return ret;
1500-
}
1501-
smu->watermarks_bitmap |= WATERMARKS_LOADED;
1489+
ret = smu_write_watermarks_table(smu);
1490+
if (ret) {
1491+
DRM_ERROR("Failed to update WMTABLE!\n");
1492+
return ret;
15021493
}
15031494

1504-
mutex_unlock(&smu->mutex);
1505-
15061495
return 0;
15071496
}
15081497

‎drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1706,35 +1706,34 @@ int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
17061706

17071707
int smu_write_watermarks_table(struct smu_context *smu)
17081708
{
1709-
void *watermarks_table = smu->smu_table.watermarks_table;
1709+
int ret = 0;
17101710

1711-
if (!watermarks_table)
1712-
return -EINVAL;
1711+
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1712+
return -EOPNOTSUPP;
17131713

1714-
return smu_update_table(smu,
1715-
SMU_TABLE_WATERMARKS,
1716-
0,
1717-
watermarks_table,
1718-
true);
1714+
mutex_lock(&smu->mutex);
1715+
1716+
ret = smu_set_watermarks_table(smu, NULL);
1717+
1718+
mutex_unlock(&smu->mutex);
1719+
1720+
return ret;
17191721
}
17201722

17211723
int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
17221724
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
17231725
{
1724-
void *table = smu->smu_table.watermarks_table;
1726+
int ret = 0;
17251727

17261728
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
17271729
return -EOPNOTSUPP;
17281730

1729-
if (!table)
1730-
return -EINVAL;
1731-
17321731
mutex_lock(&smu->mutex);
17331732

17341733
if (!smu->disable_watermark &&
17351734
smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
17361735
smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1737-
smu_set_watermarks_table(smu, table, clock_ranges);
1736+
ret = smu_set_watermarks_table(smu, clock_ranges);
17381737

17391738
if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
17401739
smu->watermarks_bitmap |= WATERMARKS_EXIST;
@@ -1744,7 +1743,7 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
17441743

17451744
mutex_unlock(&smu->mutex);
17461745

1747-
return 0;
1746+
return ret;
17481747
}
17491748

17501749
int smu_set_ac_dc(struct smu_context *smu)

‎drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -493,7 +493,7 @@ struct pptable_funcs {
493493
int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
494494
int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
495495
int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
496-
int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
496+
int (*set_watermarks_table)(struct smu_context *smu,
497497
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
498498
int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
499499
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.c

Lines changed: 50 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1577,67 +1577,65 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
15771577
}
15781578

15791579
static int navi10_set_watermarks_table(struct smu_context *smu,
1580-
void *watermarks, struct
1581-
dm_pp_wm_sets_with_clock_ranges_soc15
1582-
*clock_ranges)
1580+
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
15831581
{
1584-
int i;
1582+
Watermarks_t *table = smu->smu_table.watermarks_table;
15851583
int ret = 0;
1586-
Watermarks_t *table = watermarks;
1584+
int i;
15871585

1588-
if (!table || !clock_ranges)
1589-
return -EINVAL;
1586+
if (clock_ranges) {
1587+
if (clock_ranges->num_wm_dmif_sets > 4 ||
1588+
clock_ranges->num_wm_mcif_sets > 4)
1589+
return -EINVAL;
15901590

1591-
if (clock_ranges->num_wm_dmif_sets > 4 ||
1592-
clock_ranges->num_wm_mcif_sets > 4)
1593-
return -EINVAL;
1591+
for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1592+
table->WatermarkRow[1][i].MinClock =
1593+
cpu_to_le16((uint16_t)
1594+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1595+
1000));
1596+
table->WatermarkRow[1][i].MaxClock =
1597+
cpu_to_le16((uint16_t)
1598+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1599+
1000));
1600+
table->WatermarkRow[1][i].MinUclk =
1601+
cpu_to_le16((uint16_t)
1602+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1603+
1000));
1604+
table->WatermarkRow[1][i].MaxUclk =
1605+
cpu_to_le16((uint16_t)
1606+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1607+
1000));
1608+
table->WatermarkRow[1][i].WmSetting = (uint8_t)
1609+
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1610+
}
15941611

1595-
for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1596-
table->WatermarkRow[1][i].MinClock =
1597-
cpu_to_le16((uint16_t)
1598-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1599-
1000));
1600-
table->WatermarkRow[1][i].MaxClock =
1601-
cpu_to_le16((uint16_t)
1602-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1603-
1000));
1604-
table->WatermarkRow[1][i].MinUclk =
1605-
cpu_to_le16((uint16_t)
1606-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1607-
1000));
1608-
table->WatermarkRow[1][i].MaxUclk =
1609-
cpu_to_le16((uint16_t)
1610-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1611-
1000));
1612-
table->WatermarkRow[1][i].WmSetting = (uint8_t)
1613-
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1614-
}
1612+
for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1613+
table->WatermarkRow[0][i].MinClock =
1614+
cpu_to_le16((uint16_t)
1615+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1616+
1000));
1617+
table->WatermarkRow[0][i].MaxClock =
1618+
cpu_to_le16((uint16_t)
1619+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1620+
1000));
1621+
table->WatermarkRow[0][i].MinUclk =
1622+
cpu_to_le16((uint16_t)
1623+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1624+
1000));
1625+
table->WatermarkRow[0][i].MaxUclk =
1626+
cpu_to_le16((uint16_t)
1627+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1628+
1000));
1629+
table->WatermarkRow[0][i].WmSetting = (uint8_t)
1630+
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1631+
}
16151632

1616-
for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1617-
table->WatermarkRow[0][i].MinClock =
1618-
cpu_to_le16((uint16_t)
1619-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1620-
1000));
1621-
table->WatermarkRow[0][i].MaxClock =
1622-
cpu_to_le16((uint16_t)
1623-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1624-
1000));
1625-
table->WatermarkRow[0][i].MinUclk =
1626-
cpu_to_le16((uint16_t)
1627-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1628-
1000));
1629-
table->WatermarkRow[0][i].MaxUclk =
1630-
cpu_to_le16((uint16_t)
1631-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1632-
1000));
1633-
table->WatermarkRow[0][i].WmSetting = (uint8_t)
1634-
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1633+
smu->watermarks_bitmap |= WATERMARKS_EXIST;
16351634
}
16361635

1637-
smu->watermarks_bitmap |= WATERMARKS_EXIST;
1638-
16391636
/* pass data to smu controller */
1640-
if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1637+
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1638+
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
16411639
ret = smu_write_watermarks_table(smu);
16421640
if (ret) {
16431641
dev_err(smu->adev->dev, "Failed to update WMTABLE!");

‎drivers/gpu/drm/amd/powerplay/renoir_ppt.c

Lines changed: 42 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -841,59 +841,58 @@ static int renoir_set_performance_level(struct smu_context *smu,
841841
*/
842842
static int renoir_set_watermarks_table(
843843
struct smu_context *smu,
844-
void *watermarks,
845844
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
846845
{
847-
int i;
846+
Watermarks_t *table = smu->smu_table.watermarks_table;
848847
int ret = 0;
849-
Watermarks_t *table = watermarks;
848+
int i;
850849

851-
if (!table || !clock_ranges)
852-
return -EINVAL;
850+
if (clock_ranges) {
851+
if (clock_ranges->num_wm_dmif_sets > 4 ||
852+
clock_ranges->num_wm_mcif_sets > 4)
853+
return -EINVAL;
853854

854-
if (clock_ranges->num_wm_dmif_sets > 4 ||
855-
clock_ranges->num_wm_mcif_sets > 4)
856-
return -EINVAL;
855+
/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
856+
for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
857+
table->WatermarkRow[WM_DCFCLK][i].MinClock =
858+
cpu_to_le16((uint16_t)
859+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
860+
table->WatermarkRow[WM_DCFCLK][i].MaxClock =
861+
cpu_to_le16((uint16_t)
862+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
863+
table->WatermarkRow[WM_DCFCLK][i].MinMclk =
864+
cpu_to_le16((uint16_t)
865+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
866+
table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
867+
cpu_to_le16((uint16_t)
868+
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
869+
table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
870+
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
871+
}
857872

858-
/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
859-
for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
860-
table->WatermarkRow[WM_DCFCLK][i].MinClock =
861-
cpu_to_le16((uint16_t)
862-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
863-
table->WatermarkRow[WM_DCFCLK][i].MaxClock =
864-
cpu_to_le16((uint16_t)
865-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
866-
table->WatermarkRow[WM_DCFCLK][i].MinMclk =
867-
cpu_to_le16((uint16_t)
868-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
869-
table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
870-
cpu_to_le16((uint16_t)
871-
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
872-
table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
873-
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
874-
}
873+
for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
874+
table->WatermarkRow[WM_SOCCLK][i].MinClock =
875+
cpu_to_le16((uint16_t)
876+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
877+
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
878+
cpu_to_le16((uint16_t)
879+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
880+
table->WatermarkRow[WM_SOCCLK][i].MinMclk =
881+
cpu_to_le16((uint16_t)
882+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
883+
table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
884+
cpu_to_le16((uint16_t)
885+
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
886+
table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
887+
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
888+
}
875889

876-
for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
877-
table->WatermarkRow[WM_SOCCLK][i].MinClock =
878-
cpu_to_le16((uint16_t)
879-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
880-
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
881-
cpu_to_le16((uint16_t)
882-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
883-
table->WatermarkRow[WM_SOCCLK][i].MinMclk =
884-
cpu_to_le16((uint16_t)
885-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
886-
table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
887-
cpu_to_le16((uint16_t)
888-
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
889-
table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
890-
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
890+
smu->watermarks_bitmap |= WATERMARKS_EXIST;
891891
}
892892

893-
smu->watermarks_bitmap |= WATERMARKS_EXIST;
894-
895893
/* pass data to smu controller */
896-
if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
894+
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
895+
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
897896
ret = smu_write_watermarks_table(smu);
898897
if (ret) {
899898
dev_err(smu->adev->dev, "Failed to update WMTABLE!");

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