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+ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+ %YAML 1.2
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+ ---
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+ $id : http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
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+ $schema : http://devicetree.org/meta-schemas/core.yaml#
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+
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+ title : Marvell Global Timer (GTI) system watchdog
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+
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+ maintainers :
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+ -
Bharat Bhushan <[email protected] >
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+
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+ allOf :
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+ - $ref : watchdog.yaml#
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+
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+ properties :
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+ compatible :
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+ oneOf :
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+ - enum :
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+ - marvell,cn9670-wdt
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+ - marvell,cn10624-wdt
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+
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+ - items :
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+ - enum :
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+ - marvell,cn9880-wdt
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+ - marvell,cnf9535-wdt
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+ - const : marvell,cn9670-wdt
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+
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+ - items :
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+ - enum :
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+ - marvell,cn10308-wdt
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+ - marvell,cnf10518-wdt
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+ - const : marvell,cn10624-wdt
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+
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+ reg :
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+ maxItems : 1
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+
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+ interrupts :
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+ maxItems : 1
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+
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+ clocks :
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+ maxItems : 1
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+
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+ clock-names :
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+ items :
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+ - const : refclk
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+
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+ marvell,wdt-timer-index :
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+ $ref : /schemas/types.yaml#/definitions/uint32
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+ minimum : 0
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+ maximum : 63
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+ description :
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+ An SoC have many timers (up to 64), firmware can reserve one or more timer
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+ for some other use case and configures one of the global timer as watchdog
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+ timer. Firmware will update this field with the timer number configured
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+ as watchdog timer.
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+
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+ required :
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+ - compatible
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+ - reg
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+ - interrupts
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+ - clocks
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+ - clock-names
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+
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+ unevaluatedProperties : false
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+
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+ examples :
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+ - |
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+ #include <dt-bindings/interrupt-controller/arm-gic.h>
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ watchdog@802000040000 {
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+ compatible = "marvell,cn9670-wdt";
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+ reg = <0x00008020 0x00040000 0x00000000 0x00020000>;
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+ interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
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+ clocks = <&sclk>;
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+ clock-names = "refclk";
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+ marvell,wdt-timer-index = <63>;
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+ };
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+ };
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+
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+ ...
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