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1 parent a5a15e0 commit e84fffeCopy full SHA for e84fffe
arch/riscv/include/asm/vendor_extensions/sifive.h
@@ -8,6 +8,7 @@
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#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0
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#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1
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+#define RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF 2
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extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive;
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arch/riscv/kernel/vendor_extensions/sifive.c
@@ -9,6 +9,7 @@
/* All SiFive vendor extensions supported in Linux */
const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = {
+ __RISCV_ISA_EXT_DATA(xsfvfnrclipxfqf, RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF),
__RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD),
__RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ),
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};
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