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x86/delay: Preparatory code cleanup
The naming conventions in the delay code are confusing at best. All delay variants use a loops argument and or variable which originates from the original delay_loop() implementation. But all variants except delay_loop() are based on TSC cycles. Rename the argument to cycles and make it type u64 to avoid these weird expansions to u64 in the functions. Rename MWAITX_MAX_LOOPS to MWAITX_MAX_WAIT_CYCLES for the same reason and fixup the comment of delay_mwaitx() as well. Mark the delay_fn function pointer __ro_after_init and fixup the comment for it. No functional change and preparation for the upcoming TPAUSE based delay variant. [ Kyung Min Park: Added __init to use_tsc_delay() ] Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Kyung Min Park <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
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lines changed

arch/x86/include/asm/delay.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,9 @@
33
#define _ASM_X86_DELAY_H
44

55
#include <asm-generic/delay.h>
6+
#include <linux/init.h>
67

7-
void use_tsc_delay(void);
8+
void __init use_tsc_delay(void);
89
void use_mwaitx_delay(void);
910

1011
#endif /* _ASM_X86_DELAY_H */

arch/x86/include/asm/mwait.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020

2121
#define MWAIT_ECX_INTERRUPT_BREAK 0x1
2222
#define MWAITX_ECX_TIMER_ENABLE BIT(1)
23-
#define MWAITX_MAX_LOOPS ((u32)-1)
23+
#define MWAITX_MAX_WAIT_CYCLES UINT_MAX
2424
#define MWAITX_DISABLE_CSTATES 0xf0
2525

2626
u32 get_umwait_control_msr(void);

arch/x86/lib/delay.c

Lines changed: 24 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,19 @@
2727
# include <asm/smp.h>
2828
#endif
2929

30+
static void delay_loop(u64 __loops);
31+
32+
/*
33+
* Calibration and selection of the delay mechanism happens only once
34+
* during boot.
35+
*/
36+
static void (*delay_fn)(u64) __ro_after_init = delay_loop;
37+
3038
/* simple loop based delay: */
31-
static void delay_loop(unsigned long loops)
39+
static void delay_loop(u64 __loops)
3240
{
41+
unsigned long loops = (unsigned long)__loops;
42+
3343
asm volatile(
3444
" test %0,%0 \n"
3545
" jz 3f \n"
@@ -49,17 +59,17 @@ static void delay_loop(unsigned long loops)
4959
}
5060

5161
/* TSC based delay: */
52-
static void delay_tsc(unsigned long __loops)
62+
static void delay_tsc(u64 cycles)
5363
{
54-
u64 bclock, now, loops = __loops;
64+
u64 bclock, now;
5565
int cpu;
5666

5767
preempt_disable();
5868
cpu = smp_processor_id();
5969
bclock = rdtsc_ordered();
6070
for (;;) {
6171
now = rdtsc_ordered();
62-
if ((now - bclock) >= loops)
72+
if ((now - bclock) >= cycles)
6373
break;
6474

6575
/* Allow RT tasks to run */
@@ -77,7 +87,7 @@ static void delay_tsc(unsigned long __loops)
7787
* counter for this CPU.
7888
*/
7989
if (unlikely(cpu != smp_processor_id())) {
80-
loops -= (now - bclock);
90+
cycles -= (now - bclock);
8191
cpu = smp_processor_id();
8292
bclock = rdtsc_ordered();
8393
}
@@ -87,24 +97,24 @@ static void delay_tsc(unsigned long __loops)
8797

8898
/*
8999
* On some AMD platforms, MWAITX has a configurable 32-bit timer, that
90-
* counts with TSC frequency. The input value is the loop of the
91-
* counter, it will exit when the timer expires.
100+
* counts with TSC frequency. The input value is the number of TSC cycles
101+
* to wait. MWAITX will also exit when the timer expires.
92102
*/
93-
static void delay_mwaitx(unsigned long __loops)
103+
static void delay_mwaitx(u64 cycles)
94104
{
95-
u64 start, end, delay, loops = __loops;
105+
u64 start, end, delay;
96106

97107
/*
98108
* Timer value of 0 causes MWAITX to wait indefinitely, unless there
99109
* is a store on the memory monitored by MONITORX.
100110
*/
101-
if (loops == 0)
111+
if (!cycles)
102112
return;
103113

104114
start = rdtsc_ordered();
105115

106116
for (;;) {
107-
delay = min_t(u64, MWAITX_MAX_LOOPS, loops);
117+
delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles);
108118

109119
/*
110120
* Use cpu_tss_rw as a cacheline-aligned, seldomly
@@ -121,22 +131,15 @@ static void delay_mwaitx(unsigned long __loops)
121131

122132
end = rdtsc_ordered();
123133

124-
if (loops <= end - start)
134+
if (cycles <= end - start)
125135
break;
126136

127-
loops -= end - start;
128-
137+
cycles -= end - start;
129138
start = end;
130139
}
131140
}
132141

133-
/*
134-
* Since we calibrate only once at boot, this
135-
* function should be set once at boot and not changed
136-
*/
137-
static void (*delay_fn)(unsigned long) = delay_loop;
138-
139-
void use_tsc_delay(void)
142+
void __init use_tsc_delay(void)
140143
{
141144
if (delay_fn == delay_loop)
142145
delay_fn = delay_tsc;

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