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Ansuelandersson
Ansuel
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andersson
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clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
Rework nss_port5/6 to use the new multiple configuration implementation and correctly fix the clocks for these port under some corner case. This is particularly relevant for device that have 2.5G or 10G port connected to port5 or port 6 on ipq8074. As the parent are shared across multiple port it may be required to select the correct configuration to accomplish the desired clock. Without this patch such port doesn't work in some specific ethernet speed as the clock will be set to the wrong frequency as we just select the first configuration for the related frequency instead of selecting the best one. Signed-off-by: Christian Marangi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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‎drivers/clk/qcom/gcc-ipq8074.c

Lines changed: 76 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = {
16771677
},
16781678
};
16791679

1680-
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1681-
F(19200000, P_XO, 1, 0, 0),
1682-
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1683-
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1684-
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1685-
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1686-
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1687-
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1688-
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1680+
static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
1681+
C(P_UNIPHY1_RX, 12.5, 0, 0),
1682+
C(P_UNIPHY0_RX, 5, 0, 0),
1683+
};
1684+
1685+
static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
1686+
C(P_UNIPHY1_RX, 2.5, 0, 0),
1687+
C(P_UNIPHY0_RX, 1, 0, 0),
1688+
};
1689+
1690+
static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
1691+
FMS(19200000, P_XO, 1, 0, 0),
1692+
FM(25000000, ftbl_nss_port5_rx_clk_src_25),
1693+
FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1694+
FM(125000000, ftbl_nss_port5_rx_clk_src_125),
1695+
FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1696+
FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
16891697
{ }
16901698
};
16911699

@@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
17121720

17131721
static struct clk_rcg2 nss_port5_rx_clk_src = {
17141722
.cmd_rcgr = 0x68060,
1715-
.freq_tbl = ftbl_nss_port5_rx_clk_src,
1723+
.freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
17161724
.hid_width = 5,
17171725
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
17181726
.clkr.hw.init = &(struct clk_init_data){
17191727
.name = "nss_port5_rx_clk_src",
17201728
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
17211729
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
1722-
.ops = &clk_rcg2_ops,
1730+
.ops = &clk_rcg2_fm_ops,
17231731
},
17241732
};
17251733

@@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = {
17391747
},
17401748
};
17411749

1742-
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1743-
F(19200000, P_XO, 1, 0, 0),
1744-
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1745-
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1746-
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1747-
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1748-
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1749-
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1750-
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1750+
static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
1751+
C(P_UNIPHY1_TX, 12.5, 0, 0),
1752+
C(P_UNIPHY0_TX, 5, 0, 0),
1753+
};
1754+
1755+
static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
1756+
C(P_UNIPHY1_TX, 2.5, 0, 0),
1757+
C(P_UNIPHY0_TX, 1, 0, 0),
1758+
};
1759+
1760+
static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
1761+
FMS(19200000, P_XO, 1, 0, 0),
1762+
FM(25000000, ftbl_nss_port5_tx_clk_src_25),
1763+
FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
1764+
FM(125000000, ftbl_nss_port5_tx_clk_src_125),
1765+
FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
1766+
FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
17511767
{ }
17521768
};
17531769

@@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
17741790

17751791
static struct clk_rcg2 nss_port5_tx_clk_src = {
17761792
.cmd_rcgr = 0x68068,
1777-
.freq_tbl = ftbl_nss_port5_tx_clk_src,
1793+
.freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
17781794
.hid_width = 5,
17791795
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
17801796
.clkr.hw.init = &(struct clk_init_data){
17811797
.name = "nss_port5_tx_clk_src",
17821798
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
17831799
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
1784-
.ops = &clk_rcg2_ops,
1800+
.ops = &clk_rcg2_fm_ops,
17851801
},
17861802
};
17871803

@@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = {
18011817
},
18021818
};
18031819

1804-
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1805-
F(19200000, P_XO, 1, 0, 0),
1806-
F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1807-
F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1808-
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1809-
F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1810-
F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1811-
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1812-
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1820+
static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
1821+
C(P_UNIPHY2_RX, 5, 0, 0),
1822+
C(P_UNIPHY2_RX, 12.5, 0, 0),
1823+
};
1824+
1825+
static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
1826+
C(P_UNIPHY2_RX, 1, 0, 0),
1827+
C(P_UNIPHY2_RX, 2.5, 0, 0),
1828+
};
1829+
1830+
static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = {
1831+
FMS(19200000, P_XO, 1, 0, 0),
1832+
FM(25000000, ftbl_nss_port6_rx_clk_src_25),
1833+
FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
1834+
FM(125000000, ftbl_nss_port6_rx_clk_src_125),
1835+
FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
1836+
FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
18131837
{ }
18141838
};
18151839

@@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
18311855

18321856
static struct clk_rcg2 nss_port6_rx_clk_src = {
18331857
.cmd_rcgr = 0x68070,
1834-
.freq_tbl = ftbl_nss_port6_rx_clk_src,
1858+
.freq_multi_tbl = ftbl_nss_port6_rx_clk_src,
18351859
.hid_width = 5,
18361860
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
18371861
.clkr.hw.init = &(struct clk_init_data){
18381862
.name = "nss_port6_rx_clk_src",
18391863
.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
18401864
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
1841-
.ops = &clk_rcg2_ops,
1865+
.ops = &clk_rcg2_fm_ops,
18421866
},
18431867
};
18441868

@@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = {
18581882
},
18591883
};
18601884

1861-
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1862-
F(19200000, P_XO, 1, 0, 0),
1863-
F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1864-
F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1865-
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1866-
F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1867-
F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1868-
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1869-
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1885+
static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
1886+
C(P_UNIPHY2_TX, 5, 0, 0),
1887+
C(P_UNIPHY2_TX, 12.5, 0, 0),
1888+
};
1889+
1890+
static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
1891+
C(P_UNIPHY2_TX, 1, 0, 0),
1892+
C(P_UNIPHY2_TX, 2.5, 0, 0),
1893+
};
1894+
1895+
static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = {
1896+
FMS(19200000, P_XO, 1, 0, 0),
1897+
FM(25000000, ftbl_nss_port6_tx_clk_src_25),
1898+
FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1899+
FM(125000000, ftbl_nss_port6_tx_clk_src_125),
1900+
FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1901+
FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
18701902
{ }
18711903
};
18721904

@@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
18881920

18891921
static struct clk_rcg2 nss_port6_tx_clk_src = {
18901922
.cmd_rcgr = 0x68078,
1891-
.freq_tbl = ftbl_nss_port6_tx_clk_src,
1923+
.freq_multi_tbl = ftbl_nss_port6_tx_clk_src,
18921924
.hid_width = 5,
18931925
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
18941926
.clkr.hw.init = &(struct clk_init_data){
18951927
.name = "nss_port6_tx_clk_src",
18961928
.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
18971929
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
1898-
.ops = &clk_rcg2_ops,
1930+
.ops = &clk_rcg2_fm_ops,
18991931
},
19001932
};
19011933

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