Skip to content

Commit e8b16c7

Browse files
ambarusbroonie
authored andcommitted
spi: s3c64xx: switch gs101 to new port config data
Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. GS101 integrates 16 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. S3C64XX_SPI_ST_TX_FIFO_RDY_V2 was defined based on the USI's SPI_VERSION.USI_IP_VERSION register field, which has value 2 at reset. MAX_SPI_PORTS is updated to reflect the maximum number of ports for the rest of the compatibles. Signed-off-by: Tudor Ambarus <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
1 parent ad0adac commit e8b16c7

File tree

1 file changed

+6
-6
lines changed

1 file changed

+6
-6
lines changed

drivers/spi/spi-s3c64xx.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
#include <linux/spi/spi.h>
2121
#include <linux/types.h>
2222

23-
#define MAX_SPI_PORTS 16
23+
#define MAX_SPI_PORTS 12
2424
#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
2525
#define AUTOSUSPEND_TIMEOUT 2000
2626

@@ -79,6 +79,8 @@
7979
#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
8080
#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
8181

82+
#define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15)
83+
#define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6)
8284
#define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6
8385
#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
8486
#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
@@ -1615,11 +1617,9 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
16151617
};
16161618

16171619
static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
1618-
/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1619-
.fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
1620-
0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
1621-
/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1622-
.rx_lvl_offset = 15,
1620+
.fifo_depth = 64,
1621+
.rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2,
1622+
.tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2,
16231623
.tx_st_done = 25,
16241624
.clk_div = 4,
16251625
.high_speed = true,

0 commit comments

Comments
 (0)