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bebarinobebarino
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Merge tag 'clk-renesas-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the USB 2.0 clock selector on R-Car M3-W+ - Add support for the new RZ/G1H (R8A7742) SoC - Minor fixes and cleanups * tag 'clk-renesas-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects clk: renesas: cpg-mssr: Add R8A7742 support dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros MAINTAINERS: Add DT Bindings for Renesas Clock Generators clk: renesas: r9a06g032: Fix some typo in comments dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
2 parents 8f3d9f3 + e2f022c commit e8b81b1

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‎Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ properties:
2525
compatible:
2626
enum:
2727
- renesas,r7s9210-cpg-mssr # RZ/A2
28+
- renesas,r8a7742-cpg-mssr # RZ/G1H
2829
- renesas,r8a7743-cpg-mssr # RZ/G1M
2930
- renesas,r8a7744-cpg-mssr # RZ/G1N
3031
- renesas,r8a7745-cpg-mssr # RZ/G1E

‎Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,9 @@ Required properties:
2727
- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
2828
an R8A7795 SoC.
2929
"renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
30-
an R8A7796 SoC.
30+
an R8A77960 SoC.
31+
"renesas,r8a77961-rcar-usb2-clock-sel" if the device if a part of
32+
an R8A77961 SoC.
3133
"renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
3234
compatible device.
3335

‎MAINTAINERS

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14334,6 +14334,7 @@ M: Geert Uytterhoeven <[email protected]>
1433414334
L: [email protected]
1433514335
S: Supported
1433614336
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas
14337+
F: Documentation/devicetree/bindings/clock/renesas,*
1433714338
F: drivers/clk/renesas/
1433814339

1433914340
RENESAS EMEV2 I2C DRIVER

‎drivers/clk/renesas/Kconfig

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ config CLK_RENESAS
88
select CLK_R7S9210 if ARCH_R7S9210
99
select CLK_R8A73A4 if ARCH_R8A73A4
1010
select CLK_R8A7740 if ARCH_R8A7740
11+
select CLK_R8A7742 if ARCH_R8A7742
1112
select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
1213
select CLK_R8A7745 if ARCH_R8A7745
1314
select CLK_R8A77470 if ARCH_R8A77470
@@ -55,6 +56,10 @@ config CLK_R8A7740
5556
select CLK_RENESAS_CPG_MSTP
5657
select CLK_RENESAS_DIV6
5758

59+
config CLK_R8A7742
60+
bool "RZ/G1H clock support" if COMPILE_TEST
61+
select CLK_RCAR_GEN2_CPG
62+
5863
config CLK_R8A7743
5964
bool "RZ/G1M clock support" if COMPILE_TEST
6065
select CLK_RCAR_GEN2_CPG
@@ -90,12 +95,10 @@ config CLK_R8A7779
9095
config CLK_R8A7790
9196
bool "R-Car H2 clock support" if COMPILE_TEST
9297
select CLK_RCAR_GEN2_CPG
93-
select CLK_RENESAS_DIV6
9498

9599
config CLK_R8A7791
96100
bool "R-Car M2-W/N clock support" if COMPILE_TEST
97101
select CLK_RCAR_GEN2_CPG
98-
select CLK_RENESAS_DIV6
99102

100103
config CLK_R8A7792
101104
bool "R-Car V2H clock support" if COMPILE_TEST
@@ -104,7 +107,6 @@ config CLK_R8A7792
104107
config CLK_R8A7794
105108
bool "R-Car E2 clock support" if COMPILE_TEST
106109
select CLK_RCAR_GEN2_CPG
107-
select CLK_RENESAS_DIV6
108110

109111
config CLK_R8A7795
110112
bool "R-Car H3 clock support" if COMPILE_TEST

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ obj-$(CONFIG_CLK_RZA1) += clk-rz.o
55
obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
66
obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
77
obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
8+
obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
89
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
910
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
1011
obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o

‎drivers/clk/renesas/r8a7742-cpg-mssr.c

Lines changed: 275 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,275 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* r8a7742 Clock Pulse Generator / Module Standby and Software Reset
4+
*
5+
* Copyright (C) 2020 Renesas Electronics Corp.
6+
*/
7+
8+
#include <linux/device.h>
9+
#include <linux/init.h>
10+
#include <linux/kernel.h>
11+
#include <linux/soc/renesas/rcar-rst.h>
12+
13+
#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
14+
15+
#include "renesas-cpg-mssr.h"
16+
#include "rcar-gen2-cpg.h"
17+
18+
enum clk_ids {
19+
/* Core Clock Outputs exported to DT */
20+
LAST_DT_CORE_CLK = R8A7742_CLK_OSC,
21+
22+
/* External Input Clocks */
23+
CLK_EXTAL,
24+
CLK_USB_EXTAL,
25+
26+
/* Internal Core Clocks */
27+
CLK_MAIN,
28+
CLK_PLL0,
29+
CLK_PLL1,
30+
CLK_PLL3,
31+
CLK_PLL1_DIV2,
32+
33+
/* Module Clocks */
34+
MOD_CLK_BASE
35+
};
36+
37+
static const struct cpg_core_clk r8a7742_core_clks[] __initconst = {
38+
/* External Clock Inputs */
39+
DEF_INPUT("extal", CLK_EXTAL),
40+
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
41+
42+
/* Internal Core Clocks */
43+
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
44+
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
45+
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
46+
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
47+
48+
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
49+
50+
/* Core Clock Outputs */
51+
DEF_BASE("z", R8A7742_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
52+
DEF_BASE("lb", R8A7742_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
53+
DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
54+
DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
55+
DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
56+
DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
57+
DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
58+
59+
DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1),
60+
DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1),
61+
DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1),
62+
DEF_FIXED("zs", R8A7742_CLK_ZS, CLK_PLL1, 6, 1),
63+
DEF_FIXED("hp", R8A7742_CLK_HP, CLK_PLL1, 12, 1),
64+
DEF_FIXED("b", R8A7742_CLK_B, CLK_PLL1, 12, 1),
65+
DEF_FIXED("p", R8A7742_CLK_P, CLK_PLL1, 24, 1),
66+
DEF_FIXED("cl", R8A7742_CLK_CL, CLK_PLL1, 48, 1),
67+
DEF_FIXED("m2", R8A7742_CLK_M2, CLK_PLL1, 8, 1),
68+
DEF_FIXED("zb3", R8A7742_CLK_ZB3, CLK_PLL3, 4, 1),
69+
DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2, CLK_PLL3, 8, 1),
70+
DEF_FIXED("ddr", R8A7742_CLK_DDR, CLK_PLL3, 8, 1),
71+
DEF_FIXED("mp", R8A7742_CLK_MP, CLK_PLL1_DIV2, 15, 1),
72+
DEF_FIXED("cp", R8A7742_CLK_CP, CLK_EXTAL, 2, 1),
73+
DEF_FIXED("r", R8A7742_CLK_R, CLK_PLL1, 49152, 1),
74+
DEF_FIXED("osc", R8A7742_CLK_OSC, CLK_PLL1, 12288, 1),
75+
76+
DEF_DIV6P1("sd2", R8A7742_CLK_SD2, CLK_PLL1_DIV2, 0x078),
77+
DEF_DIV6P1("sd3", R8A7742_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
78+
DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
79+
DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
80+
};
81+
82+
static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
83+
DEF_MOD("msiof0", 0, R8A7742_CLK_MP),
84+
DEF_MOD("vcp1", 100, R8A7742_CLK_ZS),
85+
DEF_MOD("vcp0", 101, R8A7742_CLK_ZS),
86+
DEF_MOD("vpc1", 102, R8A7742_CLK_ZS),
87+
DEF_MOD("vpc0", 103, R8A7742_CLK_ZS),
88+
DEF_MOD("tmu1", 111, R8A7742_CLK_P),
89+
DEF_MOD("3dg", 112, R8A7742_CLK_ZG),
90+
DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS),
91+
DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS),
92+
DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS),
93+
DEF_MOD("fdp1-0", 119, R8A7742_CLK_ZS),
94+
DEF_MOD("tmu3", 121, R8A7742_CLK_P),
95+
DEF_MOD("tmu2", 122, R8A7742_CLK_P),
96+
DEF_MOD("cmt0", 124, R8A7742_CLK_R),
97+
DEF_MOD("tmu0", 125, R8A7742_CLK_CP),
98+
DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS),
99+
DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS),
100+
DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS),
101+
DEF_MOD("scifa2", 202, R8A7742_CLK_MP),
102+
DEF_MOD("scifa1", 203, R8A7742_CLK_MP),
103+
DEF_MOD("scifa0", 204, R8A7742_CLK_MP),
104+
DEF_MOD("msiof2", 205, R8A7742_CLK_MP),
105+
DEF_MOD("scifb0", 206, R8A7742_CLK_MP),
106+
DEF_MOD("scifb1", 207, R8A7742_CLK_MP),
107+
DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
108+
DEF_MOD("msiof3", 215, R8A7742_CLK_MP),
109+
DEF_MOD("scifb2", 216, R8A7742_CLK_MP),
110+
DEF_MOD("sys-dmac1", 218, R8A7742_CLK_ZS),
111+
DEF_MOD("sys-dmac0", 219, R8A7742_CLK_ZS),
112+
DEF_MOD("iic2", 300, R8A7742_CLK_HP),
113+
DEF_MOD("tpu0", 304, R8A7742_CLK_CP),
114+
DEF_MOD("mmcif1", 305, R8A7742_CLK_MMC1),
115+
DEF_MOD("scif2", 310, R8A7742_CLK_P),
116+
DEF_MOD("sdhi3", 311, R8A7742_CLK_SD3),
117+
DEF_MOD("sdhi2", 312, R8A7742_CLK_SD2),
118+
DEF_MOD("sdhi1", 313, R8A7742_CLK_SD1),
119+
DEF_MOD("sdhi0", 314, R8A7742_CLK_SD0),
120+
DEF_MOD("mmcif0", 315, R8A7742_CLK_MMC0),
121+
DEF_MOD("iic0", 318, R8A7742_CLK_HP),
122+
DEF_MOD("pciec", 319, R8A7742_CLK_MP),
123+
DEF_MOD("iic1", 323, R8A7742_CLK_HP),
124+
DEF_MOD("usb3.0", 328, R8A7742_CLK_MP),
125+
DEF_MOD("cmt1", 329, R8A7742_CLK_R),
126+
DEF_MOD("usbhs-dmac0", 330, R8A7742_CLK_HP),
127+
DEF_MOD("usbhs-dmac1", 331, R8A7742_CLK_HP),
128+
DEF_MOD("rwdt", 402, R8A7742_CLK_R),
129+
DEF_MOD("irqc", 407, R8A7742_CLK_CP),
130+
DEF_MOD("intc-sys", 408, R8A7742_CLK_ZS),
131+
DEF_MOD("audio-dmac1", 501, R8A7742_CLK_HP),
132+
DEF_MOD("audio-dmac0", 502, R8A7742_CLK_HP),
133+
DEF_MOD("thermal", 522, CLK_EXTAL),
134+
DEF_MOD("pwm", 523, R8A7742_CLK_P),
135+
DEF_MOD("usb-ehci", 703, R8A7742_CLK_MP),
136+
DEF_MOD("usbhs", 704, R8A7742_CLK_HP),
137+
DEF_MOD("hscif1", 716, R8A7742_CLK_ZS),
138+
DEF_MOD("hscif0", 717, R8A7742_CLK_ZS),
139+
DEF_MOD("scif1", 720, R8A7742_CLK_P),
140+
DEF_MOD("scif0", 721, R8A7742_CLK_P),
141+
DEF_MOD("du2", 722, R8A7742_CLK_ZX),
142+
DEF_MOD("du1", 723, R8A7742_CLK_ZX),
143+
DEF_MOD("du0", 724, R8A7742_CLK_ZX),
144+
DEF_MOD("lvds1", 725, R8A7742_CLK_ZX),
145+
DEF_MOD("lvds0", 726, R8A7742_CLK_ZX),
146+
DEF_MOD("r-gp2d", 807, R8A7742_CLK_ZX),
147+
DEF_MOD("vin3", 808, R8A7742_CLK_ZG),
148+
DEF_MOD("vin2", 809, R8A7742_CLK_ZG),
149+
DEF_MOD("vin1", 810, R8A7742_CLK_ZG),
150+
DEF_MOD("vin0", 811, R8A7742_CLK_ZG),
151+
DEF_MOD("etheravb", 812, R8A7742_CLK_HP),
152+
DEF_MOD("ether", 813, R8A7742_CLK_P),
153+
DEF_MOD("sata1", 814, R8A7742_CLK_ZS),
154+
DEF_MOD("sata0", 815, R8A7742_CLK_ZS),
155+
DEF_MOD("imr-x2-1", 820, R8A7742_CLK_ZG),
156+
DEF_MOD("imr-x2-0", 821, R8A7742_CLK_HP),
157+
DEF_MOD("imr-lsx2-1", 822, R8A7742_CLK_P),
158+
DEF_MOD("imr-lsx2-0", 823, R8A7742_CLK_ZS),
159+
DEF_MOD("gpio5", 907, R8A7742_CLK_CP),
160+
DEF_MOD("gpio4", 908, R8A7742_CLK_CP),
161+
DEF_MOD("gpio3", 909, R8A7742_CLK_CP),
162+
DEF_MOD("gpio2", 910, R8A7742_CLK_CP),
163+
DEF_MOD("gpio1", 911, R8A7742_CLK_CP),
164+
DEF_MOD("gpio0", 912, R8A7742_CLK_CP),
165+
DEF_MOD("can1", 915, R8A7742_CLK_P),
166+
DEF_MOD("can0", 916, R8A7742_CLK_P),
167+
DEF_MOD("qspi_mod", 917, R8A7742_CLK_QSPI),
168+
DEF_MOD("iicdvfs", 926, R8A7742_CLK_CP),
169+
DEF_MOD("i2c3", 928, R8A7742_CLK_HP),
170+
DEF_MOD("i2c2", 929, R8A7742_CLK_HP),
171+
DEF_MOD("i2c1", 930, R8A7742_CLK_HP),
172+
DEF_MOD("i2c0", 931, R8A7742_CLK_HP),
173+
DEF_MOD("ssi-all", 1005, R8A7742_CLK_P),
174+
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
175+
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
176+
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
177+
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
178+
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
179+
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
180+
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
181+
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
182+
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
183+
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
184+
DEF_MOD("scu-all", 1017, R8A7742_CLK_P),
185+
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
186+
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
187+
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
188+
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
189+
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
190+
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
191+
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
192+
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
193+
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
194+
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
195+
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
196+
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
197+
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
198+
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
199+
};
200+
201+
static const unsigned int r8a7742_crit_mod_clks[] __initconst = {
202+
MOD_CLK_ID(402), /* RWDT */
203+
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
204+
};
205+
206+
/*
207+
* CPG Clock Data
208+
*/
209+
210+
/*
211+
* MD EXTAL PLL0 PLL1 PLL3
212+
* 14 13 19 (MHz) *1 *1
213+
*---------------------------------------------------
214+
* 0 0 0 15 x172/2 x208/2 x106
215+
* 0 0 1 15 x172/2 x208/2 x88
216+
* 0 1 0 20 x130/2 x156/2 x80
217+
* 0 1 1 20 x130/2 x156/2 x66
218+
* 1 0 0 26 / 2 x200/2 x240/2 x122
219+
* 1 0 1 26 / 2 x200/2 x240/2 x102
220+
* 1 1 0 30 / 2 x172/2 x208/2 x106
221+
* 1 1 1 30 / 2 x172/2 x208/2 x88
222+
*
223+
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
224+
*/
225+
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
226+
(((md) & BIT(13)) >> 12) | \
227+
(((md) & BIT(19)) >> 19))
228+
229+
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
230+
/* EXTAL div PLL1 mult PLL3 mult */
231+
{ 1, 208, 106, },
232+
{ 1, 208, 88, },
233+
{ 1, 156, 80, },
234+
{ 1, 156, 66, },
235+
{ 2, 240, 122, },
236+
{ 2, 240, 102, },
237+
{ 2, 208, 106, },
238+
{ 2, 208, 88, },
239+
};
240+
241+
static int __init r8a7742_cpg_mssr_init(struct device *dev)
242+
{
243+
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
244+
u32 cpg_mode;
245+
int error;
246+
247+
error = rcar_rst_read_mode_pins(&cpg_mode);
248+
if (error)
249+
return error;
250+
251+
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
252+
253+
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
254+
}
255+
256+
const struct cpg_mssr_info r8a7742_cpg_mssr_info __initconst = {
257+
/* Core Clocks */
258+
.core_clks = r8a7742_core_clks,
259+
.num_core_clks = ARRAY_SIZE(r8a7742_core_clks),
260+
.last_dt_core_clk = LAST_DT_CORE_CLK,
261+
.num_total_core_clks = MOD_CLK_BASE,
262+
263+
/* Module Clocks */
264+
.mod_clks = r8a7742_mod_clks,
265+
.num_mod_clks = ARRAY_SIZE(r8a7742_mod_clks),
266+
.num_hw_mod_clks = 12 * 32,
267+
268+
/* Critical Module Clocks */
269+
.crit_mod_clks = r8a7742_crit_mod_clks,
270+
.num_crit_mod_clks = ARRAY_SIZE(r8a7742_crit_mod_clks),
271+
272+
/* Callbacks */
273+
.init = r8a7742_cpg_mssr_init,
274+
.cpg_clk_register = rcar_gen2_cpg_clk_register,
275+
};

‎drivers/clk/renesas/r9a06g032-clocks.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0
22
/*
3-
* R9A09G032 clock driver
3+
* R9A06G032 clock driver
44
*
55
* Copyright (C) 2018 Renesas Electronics Europe Limited
66
*
@@ -338,8 +338,8 @@ clk_rdesc_get(struct r9a06g032_priv *clocks,
338338
}
339339

340340
/*
341-
* This implements the R9A09G032 clock gate 'driver'. We cannot use the system's
342-
* clock gate framework as the gates on the R9A09G032 have a special enabling
341+
* This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
342+
* clock gate framework as the gates on the R9A06G032 have a special enabling
343343
* sequence, therefore we use this little proxy.
344344
*/
345345
struct r9a06g032_clk_gate {

‎drivers/clk/renesas/renesas-cpg-mssr.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -673,6 +673,12 @@ static const struct of_device_id cpg_mssr_match[] = {
673673
.data = &r7s9210_cpg_mssr_info,
674674
},
675675
#endif
676+
#ifdef CONFIG_CLK_R8A7742
677+
{
678+
.compatible = "renesas,r8a7742-cpg-mssr",
679+
.data = &r8a7742_cpg_mssr_info,
680+
},
681+
#endif
676682
#ifdef CONFIG_CLK_R8A7743
677683
{
678684
.compatible = "renesas,r8a7743-cpg-mssr",

‎drivers/clk/renesas/renesas-cpg-mssr.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,7 @@ struct cpg_mssr_info {
155155
};
156156

157157
extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
158+
extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
158159
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
159160
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
160161
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;

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