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moonlinuxvinodkoul
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phy: rockchip-pcie: Use devm_clk_get_enabled() helper
Use devm_clk_get_enabled() instead of devm_clk_get() to make the code cleaner and avoid calling clk_disable_unprepare(), as this is exactly what this function does. Use the dev_err_probe() helper to simplify error handling during probe. Refactor the mutex handling in the rockchip_pcie_phy_init() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_assert() function, with 0 indicating success and an error code indicating failure Signed-off-by: Anand Moon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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drivers/phy/rockchip/phy-rockchip-pcie.c

Lines changed: 10 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -274,30 +274,19 @@ static int rockchip_pcie_phy_init(struct phy *phy)
274274

275275
mutex_lock(&rk_phy->pcie_mutex);
276276

277-
if (rk_phy->init_cnt++)
278-
goto err_out;
279-
280-
err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
281-
if (err) {
282-
dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
283-
goto err_refclk;
277+
if (rk_phy->init_cnt++) {
278+
mutex_unlock(&rk_phy->pcie_mutex);
279+
return 0;
284280
}
285281

286282
err = reset_control_assert(rk_phy->phy_rst);
287283
if (err) {
288284
dev_err(&phy->dev, "assert phy_rst err %d\n", err);
289-
goto err_reset;
285+
rk_phy->init_cnt--;
286+
mutex_unlock(&rk_phy->pcie_mutex);
287+
return err;
290288
}
291289

292-
err_out:
293-
mutex_unlock(&rk_phy->pcie_mutex);
294-
return 0;
295-
296-
err_reset:
297-
298-
clk_disable_unprepare(rk_phy->clk_pciephy_ref);
299-
err_refclk:
300-
rk_phy->init_cnt--;
301290
mutex_unlock(&rk_phy->pcie_mutex);
302291
return err;
303292
}
@@ -312,8 +301,6 @@ static int rockchip_pcie_phy_exit(struct phy *phy)
312301
if (--rk_phy->init_cnt)
313302
goto err_init_cnt;
314303

315-
clk_disable_unprepare(rk_phy->clk_pciephy_ref);
316-
317304
err_init_cnt:
318305
mutex_unlock(&rk_phy->pcie_mutex);
319306
return 0;
@@ -375,11 +362,10 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev)
375362
return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst),
376363
"missing phy property for reset controller\n");
377364

378-
rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
379-
if (IS_ERR(rk_phy->clk_pciephy_ref)) {
380-
dev_err(dev, "refclk not found.\n");
381-
return PTR_ERR(rk_phy->clk_pciephy_ref);
382-
}
365+
rk_phy->clk_pciephy_ref = devm_clk_get_enabled(dev, "refclk");
366+
if (IS_ERR(rk_phy->clk_pciephy_ref))
367+
return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->clk_pciephy_ref),
368+
"failed to get phyclk\n");
383369

384370
/* parse #phy-cells to see if it's legacy PHY model */
385371
if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))

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