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Merge tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Remove obsolete clock DT binding header files - Add Battery Backup (VBATTB) and I2C clocks, resets, and power domains on RZ/G3S - Add audio clocks on R-Car V4M - Add video capture (ISPCS, CSI-2, VIN) clocks on R-Car V4M - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C clk: renesas: r8a779h0: Add Audio clocks clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP dt-bindings: clock: rcar-gen2: Remove obsolete header files dt-bindings: clock: r8a7779: Remove duplicate newline clk: renesas: Drop "Renesas" from individual driver descriptions clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments clk: renesas: r8a779h0: Add VIN clocks dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock clk: renesas: r8a77970: Use common cpg_lock clk: renesas: r8a779h0: Add CSI-2 clocks clk: renesas: r8a779h0: Add ISPCS clocks
2 parents 1613e60 + c7e5884 commit e96b042

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15 files changed

+57
-732
lines changed

15 files changed

+57
-732
lines changed

‎Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ properties:
6262

6363
'#reset-cells':
6464
description:
65-
The single reset specifier cell must be the module number, as defined in
65+
The single reset specifier cell must be the reset number, as defined in
6666
<dt-bindings/clock/r9a0*-cpg.h>.
6767
const: 1
6868

‎drivers/clk/renesas/Kconfig

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -218,14 +218,14 @@ config CLK_RCAR_GEN4_CPG
218218
select CLK_RENESAS_CPG_MSSR
219219

220220
config CLK_RCAR_USB2_CLOCK_SEL
221-
bool "Renesas R-Car USB2 clock selector support"
221+
bool "R-Car USB2 clock selector support"
222222
depends on ARCH_RENESAS || COMPILE_TEST
223223
select RESET_CONTROLLER
224224
help
225225
This is a driver for R-Car USB2 clock selector
226226

227227
config CLK_RZG2L
228-
bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
228+
bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
229229
select RESET_CONTROLLER
230230

231231
# Generic

‎drivers/clk/renesas/r8a77970-cpg-mssr.c

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
1919

2020
#include "renesas-cpg-mssr.h"
21+
#include "rcar-cpg-lib.h"
2122
#include "rcar-gen3-cpg.h"
2223

2324
#define CPG_SD0CKCR 0x0074
@@ -47,8 +48,6 @@ enum clk_ids {
4748
MOD_CLK_BASE
4849
};
4950

50-
static spinlock_t cpg_lock;
51-
5251
static const struct clk_div_table cpg_sd0h_div_table[] = {
5352
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
5453
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
@@ -213,8 +212,6 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev)
213212
if (error)
214213
return error;
215214

216-
spin_lock_init(&cpg_lock);
217-
218215
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
219216

220217
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);

‎drivers/clk/renesas/r8a779h0-cpg-mssr.c

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
176176
DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
177177
DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
178178
DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
179+
DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
180+
DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
179181
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
180182
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
181183
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
@@ -185,6 +187,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
185187
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
186188
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
187189
DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
190+
DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO),
191+
DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO),
188192
DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
189193
DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
190194
DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
@@ -204,6 +208,22 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
204208
DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
205209
DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
206210
DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
211+
DEF_MOD("vin00", 730, R8A779H0_CLK_S0D4_VIO),
212+
DEF_MOD("vin01", 731, R8A779H0_CLK_S0D4_VIO),
213+
DEF_MOD("vin02", 800, R8A779H0_CLK_S0D4_VIO),
214+
DEF_MOD("vin03", 801, R8A779H0_CLK_S0D4_VIO),
215+
DEF_MOD("vin04", 802, R8A779H0_CLK_S0D4_VIO),
216+
DEF_MOD("vin05", 803, R8A779H0_CLK_S0D4_VIO),
217+
DEF_MOD("vin06", 804, R8A779H0_CLK_S0D4_VIO),
218+
DEF_MOD("vin07", 805, R8A779H0_CLK_S0D4_VIO),
219+
DEF_MOD("vin10", 806, R8A779H0_CLK_S0D4_VIO),
220+
DEF_MOD("vin11", 807, R8A779H0_CLK_S0D4_VIO),
221+
DEF_MOD("vin12", 808, R8A779H0_CLK_S0D4_VIO),
222+
DEF_MOD("vin13", 809, R8A779H0_CLK_S0D4_VIO),
223+
DEF_MOD("vin14", 810, R8A779H0_CLK_S0D4_VIO),
224+
DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO),
225+
DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO),
226+
DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO),
207227
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
208228
DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
209229
DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
@@ -213,6 +233,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
213233
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
214234
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
215235
DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
236+
DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER),
237+
DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER),
216238
};
217239

218240
/*
@@ -222,10 +244,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
222244
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
223245
* 14 13 (MHz)
224246
* ------------------------------------------------------------------------
225-
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
226-
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
247+
* 0 0 16.66 / 1 x192 x240 x192 x240 x192 x168 /16
248+
* 0 1 20 / 1 x160 x200 x160 x200 x160 x140 /19
227249
* 1 0 Prohibited setting
228-
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
250+
* 1 1 33.33 / 2 x192 x240 x192 x240 x192 x168 /32
229251
*/
230252
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
231253
(((md) & BIT(13)) >> 13))

‎drivers/clk/renesas/r9a08g045-cpg.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,8 +213,13 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
213213
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
214214
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
215215
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
216+
DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
217+
DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
218+
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
219+
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
216220
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
217221
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
222+
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
218223
};
219224

220225
static const struct rzg2l_reset r9a08g045_resets[] = {
@@ -227,17 +232,23 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
227232
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
228233
DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
229234
DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
235+
DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
236+
DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),
237+
DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
238+
DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
230239
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
231240
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
232241
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
233242
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
243+
DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
234244
};
235245

236246
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
237247
MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
238248
MOD_CLK_BASE + R9A08G045_IA55_PCLK,
239249
MOD_CLK_BASE + R9A08G045_IA55_CLK,
240250
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
251+
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
241252
};
242253

243254
static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
@@ -272,9 +283,24 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
272283
DEF_PD("eth1", R9A08G045_PD_ETHER1,
273284
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
274285
RZG2L_PD_F_NONE),
286+
DEF_PD("i2c0", R9A08G045_PD_I2C0,
287+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),
288+
RZG2L_PD_F_NONE),
289+
DEF_PD("i2c1", R9A08G045_PD_I2C1,
290+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),
291+
RZG2L_PD_F_NONE),
292+
DEF_PD("i2c2", R9A08G045_PD_I2C2,
293+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),
294+
RZG2L_PD_F_NONE),
295+
DEF_PD("i2c3", R9A08G045_PD_I2C3,
296+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),
297+
RZG2L_PD_F_NONE),
275298
DEF_PD("scif0", R9A08G045_PD_SCIF0,
276299
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
277300
RZG2L_PD_F_NONE),
301+
DEF_PD("vbat", R9A08G045_PD_VBAT,
302+
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
303+
RZG2L_PD_F_ALWAYS_ON),
278304
};
279305

280306
const struct rzg2l_cpg_info r9a08g045_cpg_info = {

‎drivers/clk/renesas/rcar-cpg-lib.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222

2323
#include "rcar-cpg-lib.h"
2424

25-
spinlock_t cpg_lock;
25+
DEFINE_SPINLOCK(cpg_lock);
2626

2727
void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
2828
{

‎drivers/clk/renesas/rcar-gen2-cpg.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@
3030
#define CPG_ADSPCKCR 0x025c
3131
#define CPG_RCANCKCR 0x0270
3232

33-
static spinlock_t cpg_lock;
33+
static DEFINE_SPINLOCK(cpg_lock);
3434

3535
/*
3636
* Z Clock
@@ -387,7 +387,5 @@ int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
387387
cpg_quirks = (uintptr_t)attr->data;
388388
pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
389389

390-
spin_lock_init(&cpg_lock);
391-
392390
return 0;
393391
}

‎drivers/clk/renesas/rcar-gen3-cpg.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -551,7 +551,5 @@ int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
551551
cpg_quirks = (uintptr_t)attr->data;
552552
pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
553553

554-
spin_lock_init(&cpg_lock);
555-
556554
return 0;
557555
}

‎drivers/clk/renesas/rcar-gen4-cpg.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -466,7 +466,5 @@ int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
466466
cpg_clk_extalr = clk_extalr;
467467
cpg_mode = mode;
468468

469-
spin_lock_init(&cpg_lock);
470-
471469
return 0;
472470
}

‎include/dt-bindings/clock/r8a7779-clock.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,5 +57,4 @@
5757
#define R8A7779_CLK_MMC1 30
5858
#define R8A7779_CLK_MMC0 31
5959

60-
6160
#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */

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