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dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings
Add clock definitions for the main clock and reset controllers of MT6735 (apmixedsys, topckgen, infracfg and pericfg). Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml

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description:
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The Mediatek apmixedsys controller provides PLLs to the system.
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The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
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The clock values can be found in <dt-bindings/clock/mt*-clk.h>
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and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.
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properties:
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compatible:
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- enum:
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- mediatek,mt2701-apmixedsys
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- mediatek,mt2712-apmixedsys
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- mediatek,mt6735-apmixedsys
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- mediatek,mt6765-apmixedsys
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- mediatek,mt6779-apmixed
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- mediatek,mt6795-apmixedsys

‎Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml

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description:
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The Mediatek infracfg controller provides various clocks and reset outputs
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to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
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and reset values in <dt-bindings/reset/mt*-reset.h> and
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<dt-bindings/reset/mt*-resets.h>.
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to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>
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and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
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<dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and
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<dt-bindings/reset/mediatek,mt*-infracfg.h>.
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properties:
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- enum:
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- mediatek,mt2701-infracfg
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- mediatek,mt2712-infracfg
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- mediatek,mt6735-infracfg
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- mediatek,mt6765-infracfg
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- mediatek,mt6795-infracfg
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- mediatek,mt6779-infracfg_ao

‎Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml

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- enum:
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- mediatek,mt2701-pericfg
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- mediatek,mt2712-pericfg
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- mediatek,mt6735-pericfg
2324
- mediatek,mt6765-pericfg
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- mediatek,mt6795-pericfg
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- mediatek,mt7622-pericfg

‎Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml

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description:
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The Mediatek topckgen controller provides various clocks to the system.
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The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
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The clock values can be found in <dt-bindings/clock/mt*-clk.h> and
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<dt-bindings/clock/mediatek,mt*-topckgen.h>.
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properties:
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compatible:
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- enum:
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- mediatek,mt2701-topckgen
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- mediatek,mt2712-topckgen
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- mediatek,mt6735-topckgen
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- mediatek,mt6765-topckgen
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- mediatek,mt6779-topckgen
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- mediatek,mt6795-topckgen

‎MAINTAINERS

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F: Documentation/devicetree/bindings/mmc/mtk-sd.yaml
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F: drivers/mmc/host/mtk-sd.c
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MEDIATEK MT6735 CLOCK & RESET DRIVERS
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M: Yassine Oudjana <[email protected]>
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L: [email protected]
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
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F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
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F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
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F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
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F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
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F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
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MEDIATEK MT76 WIRELESS LAN DRIVER
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M: Felix Fietkau <[email protected]>
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M: Lorenzo Bianconi <[email protected]>

‎include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
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#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIVPLL 2
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#define CLK_APMIXED_MMPLL 3
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#define CLK_APMIXED_MSDCPLL 4
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#define CLK_APMIXED_VENCPLL 5
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#define CLK_APMIXED_TVDPLL 6
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#define CLK_APMIXED_APLL1 7
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#define CLK_APMIXED_APLL2 8
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#endif

‎include/dt-bindings/clock/mediatek,mt6735-infracfg.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
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#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H
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#define CLK_INFRA_DBG 0
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#define CLK_INFRA_GCE 1
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#define CLK_INFRA_TRBG 2
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#define CLK_INFRA_CPUM 3
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#define CLK_INFRA_DEVAPC 4
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#define CLK_INFRA_AUDIO 5
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#define CLK_INFRA_GCPU 6
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#define CLK_INFRA_L2C_SRAM 7
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#define CLK_INFRA_M4U 8
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#define CLK_INFRA_CLDMA 9
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#define CLK_INFRA_CONNMCU_BUS 10
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#define CLK_INFRA_KP 11
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#define CLK_INFRA_APXGPT 12
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#define CLK_INFRA_SEJ 13
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#define CLK_INFRA_CCIF0_AP 14
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#define CLK_INFRA_CCIF1_AP 15
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#define CLK_INFRA_PMIC_SPI 16
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#define CLK_INFRA_PMIC_WRAP 17
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#endif

‎include/dt-bindings/clock/mediatek,mt6735-pericfg.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H
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#define _DT_BINDINGS_CLK_MT6735_PERICFG_H
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#define CLK_PERI_DISP_PWM 0
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#define CLK_PERI_THERM 1
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#define CLK_PERI_PWM1 2
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#define CLK_PERI_PWM2 3
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#define CLK_PERI_PWM3 4
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#define CLK_PERI_PWM4 5
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#define CLK_PERI_PWM5 6
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#define CLK_PERI_PWM6 7
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#define CLK_PERI_PWM7 8
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#define CLK_PERI_PWM 9
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#define CLK_PERI_USB0 10
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#define CLK_PERI_IRDA 11
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#define CLK_PERI_APDMA 12
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#define CLK_PERI_MSDC30_0 13
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#define CLK_PERI_MSDC30_1 14
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#define CLK_PERI_MSDC30_2 15
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#define CLK_PERI_MSDC30_3 16
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#define CLK_PERI_UART0 17
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#define CLK_PERI_UART1 18
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#define CLK_PERI_UART2 19
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#define CLK_PERI_UART3 20
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#define CLK_PERI_UART4 21
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#define CLK_PERI_BTIF 22
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#define CLK_PERI_I2C0 23
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#define CLK_PERI_I2C1 24
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#define CLK_PERI_I2C2 25
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#define CLK_PERI_I2C3 26
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#define CLK_PERI_AUXADC 27
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#define CLK_PERI_SPI0 28
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#define CLK_PERI_IRTX 29
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#endif

‎include/dt-bindings/clock/mediatek,mt6735-topckgen.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
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#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
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#define CLK_TOP_AD_SYS_26M_CK 0
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#define CLK_TOP_CLKPH_MCK_O 1
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#define CLK_TOP_DMPLL 2
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#define CLK_TOP_DPI_CK 3
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#define CLK_TOP_WHPLL_AUDIO_CK 4
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#define CLK_TOP_SYSPLL_D2 5
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#define CLK_TOP_SYSPLL_D3 6
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#define CLK_TOP_SYSPLL_D5 7
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#define CLK_TOP_SYSPLL1_D2 8
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#define CLK_TOP_SYSPLL1_D4 9
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#define CLK_TOP_SYSPLL1_D8 10
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#define CLK_TOP_SYSPLL1_D16 11
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#define CLK_TOP_SYSPLL2_D2 12
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#define CLK_TOP_SYSPLL2_D4 13
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#define CLK_TOP_SYSPLL3_D2 14
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#define CLK_TOP_SYSPLL3_D4 15
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#define CLK_TOP_SYSPLL4_D2 16
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#define CLK_TOP_SYSPLL4_D4 17
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#define CLK_TOP_UNIVPLL_D2 18
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#define CLK_TOP_UNIVPLL_D3 19
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#define CLK_TOP_UNIVPLL_D5 20
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#define CLK_TOP_UNIVPLL_D26 21
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#define CLK_TOP_UNIVPLL1_D2 22
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#define CLK_TOP_UNIVPLL1_D4 23
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#define CLK_TOP_UNIVPLL1_D8 24
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#define CLK_TOP_UNIVPLL2_D2 25
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#define CLK_TOP_UNIVPLL2_D4 26
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#define CLK_TOP_UNIVPLL2_D8 27
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#define CLK_TOP_UNIVPLL3_D2 28
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#define CLK_TOP_UNIVPLL3_D4 29
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#define CLK_TOP_MSDCPLL_D2 30
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#define CLK_TOP_MSDCPLL_D4 31
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#define CLK_TOP_MSDCPLL_D8 32
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#define CLK_TOP_MSDCPLL_D16 33
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#define CLK_TOP_VENCPLL_D3 34
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#define CLK_TOP_TVDPLL_D2 35
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#define CLK_TOP_TVDPLL_D4 36
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#define CLK_TOP_DMPLL_D2 37
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#define CLK_TOP_DMPLL_D4 38
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#define CLK_TOP_DMPLL_D8 39
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#define CLK_TOP_AD_SYS_26M_D2 40
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#define CLK_TOP_AXI_SEL 41
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#define CLK_TOP_MEM_SEL 42
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#define CLK_TOP_DDRPHY_SEL 43
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#define CLK_TOP_MM_SEL 44
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#define CLK_TOP_PWM_SEL 45
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#define CLK_TOP_VDEC_SEL 46
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#define CLK_TOP_MFG_SEL 47
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#define CLK_TOP_CAMTG_SEL 48
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#define CLK_TOP_UART_SEL 49
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#define CLK_TOP_SPI_SEL 50
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#define CLK_TOP_USB20_SEL 51
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#define CLK_TOP_MSDC50_0_SEL 52
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#define CLK_TOP_MSDC30_0_SEL 53
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#define CLK_TOP_MSDC30_1_SEL 54
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#define CLK_TOP_MSDC30_2_SEL 55
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#define CLK_TOP_MSDC30_3_SEL 56
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#define CLK_TOP_AUDIO_SEL 57
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#define CLK_TOP_AUDINTBUS_SEL 58
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#define CLK_TOP_PMICSPI_SEL 59
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#define CLK_TOP_SCP_SEL 60
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#define CLK_TOP_ATB_SEL 61
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#define CLK_TOP_DPI0_SEL 62
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#define CLK_TOP_SCAM_SEL 63
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#define CLK_TOP_MFG13M_SEL 64
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#define CLK_TOP_AUD1_SEL 65
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#define CLK_TOP_AUD2_SEL 66
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#define CLK_TOP_IRDA_SEL 67
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#define CLK_TOP_IRTX_SEL 68
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#define CLK_TOP_DISPPWM_SEL 69
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#endif

‎include/dt-bindings/reset/mediatek,mt6735-infracfg.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H
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#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H
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#define MT6735_INFRA_RST0_EMI_REG 0
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#define MT6735_INFRA_RST0_DRAMC0_AO 1
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#define MT6735_INFRA_RST0_AP_CIRQ_EINT 2
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#define MT6735_INFRA_RST0_APXGPT 3
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#define MT6735_INFRA_RST0_SCPSYS 4
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#define MT6735_INFRA_RST0_KP 5
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#define MT6735_INFRA_RST0_PMIC_WRAP 6
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#define MT6735_INFRA_RST0_CLDMA_AO_TOP 7
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#define MT6735_INFRA_RST0_USBSIF_TOP 8
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#define MT6735_INFRA_RST0_EMI 9
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#define MT6735_INFRA_RST0_CCIF 10
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#define MT6735_INFRA_RST0_DRAMC0 11
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#define MT6735_INFRA_RST0_EMI_AO_REG 12
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#define MT6735_INFRA_RST0_CCIF_AO 13
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#define MT6735_INFRA_RST0_TRNG 14
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#define MT6735_INFRA_RST0_SYS_CIRQ 15
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#define MT6735_INFRA_RST0_GCE 16
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#define MT6735_INFRA_RST0_M4U 17
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#define MT6735_INFRA_RST0_CCIF1 18
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#define MT6735_INFRA_RST0_CLDMA_TOP_PD 19
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#endif

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