@@ -358,9 +358,8 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
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/*
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* Mask B, Pentium, but not Pentium MMX
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*/
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- if (c -> x86 == 5 &&
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- c -> x86_stepping >= 1 && c -> x86_stepping <= 4 &&
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- c -> x86_model <= 3 ) {
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+ if (c -> x86_vfm >= INTEL_FAM5_START && c -> x86_vfm < INTEL_PENTIUM_MMX &&
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+ c -> x86_stepping >= 1 && c -> x86_stepping <= 4 ) {
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/*
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* Remember we have B step Pentia with bugs
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*/
@@ -387,7 +386,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
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* The Quark is also family 5, but does not have the same bug.
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*/
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clear_cpu_bug (c , X86_BUG_F00F );
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- if (c -> x86 == 5 && c -> x86_model < 9 ) {
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+ if (c -> x86_vfm >= INTEL_FAM5_START && c -> x86_vfm < INTEL_QUARK_X1000 ) {
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static int f00f_workaround_enabled ;
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set_cpu_bug (c , X86_BUG_F00F );
@@ -435,7 +434,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
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* integrated APIC (see 11AP erratum in "Pentium Processor
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* Specification Update").
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*/
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- if (boot_cpu_has (X86_FEATURE_APIC ) && ( c -> x86 << 8 | c -> x86_model << 4 ) == 0x520 &&
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+ if (boot_cpu_has (X86_FEATURE_APIC ) && c -> x86_vfm == INTEL_PENTIUM_75 &&
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(c -> x86_stepping < 0x6 || c -> x86_stepping == 0xb ))
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set_cpu_bug (c , X86_BUG_11AP );
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@@ -612,7 +611,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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* Intel Quark SoC X1000 contains a 4-way set associative
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* 16K cache with a 16 byte cache line and 256 lines per tag
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*/
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- if (( c -> x86 == 5 ) && ( c -> x86_model == 9 ) )
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+ if (c -> x86_vfm == INTEL_QUARK_X1000 )
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size = 16 ;
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return size ;
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}
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