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Merge tag 'mailbox-v5.14' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar: - imx: add support for i.MX8ULP - mtk: code change around callback struct - qcom: add sm6125, MSM8939 fix for channel exhaustion - microchip: add support for polarfire controller - misc: cosmetic changes to bcm-2835,flexrm,pdc, arm-mhu and hisilicon * tag 'mailbox-v5.14' of git://git.linaro.org/landing-teams/working/fujitsu/integration: (26 commits) MAINTAINERS: add entry for polarfire soc mailbox dt-bindings: add bindings for polarfire soc system controller mbox: add polarfire soc system controller mailbox dt-bindings: add bindings for polarfire soc mailbox mailbox: imx: Avoid using val uninitialized in imx_mu_isr() mailbox: qcom: Add MSM8939 APCS support mailbox: qcom: Use PLATFORM_DEVID_AUTO to register platform device dt-bindings: mailbox: qcom: Add MSM8939 APCS compatible mailbox: qcom-apcs: Add SM6125 compatible dt-bindings: mailbox: Add binding for sm6125 mailbox: mtk-cmdq: Fix uninitialized variable in cmdq_mbox_flush() mailbox: bcm-flexrm-mailbox: Remove redundant dev_err call in flexrm_mbox_probe() mailbox: bcm2835: Remove redundant dev_err call in bcm2835_mbox_probe() mailbox: qcom-ipcc: Fix IPCC mbox channel exhaustion mailbox: mtk-cmdq: Add struct cmdq_pkt in struct cmdq_cb_data mailbox: mtk-cmdq: Use mailbox rx_callback mailbox: mtk-cmdq: Remove cmdq_cb_status mailbox: imx-mailbox: support i.MX8ULP MU mailbox: imx: add xSR/xCR register array mailbox: imx: replace the xTR/xRR array with single register ...
2 parents c0c6d20 + 4f19718 commit ebb81c1

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-102
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‎Documentation/devicetree/bindings/mailbox/fsl,mu.yaml

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@@ -26,6 +26,7 @@ properties:
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oneOf:
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- const: fsl,imx6sx-mu
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- const: fsl,imx7ulp-mu
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- const: fsl,imx8ulp-mu
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- const: fsl,imx8-mu-scu
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- items:
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- enum:

‎Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
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maintainers:
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- Conor Dooley <[email protected]>
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properties:
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compatible:
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const: microchip,polarfire-soc-mailbox
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reg:
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items:
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- description: mailbox data registers
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- description: mailbox interrupt registers
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interrupts:
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maxItems: 1
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"#mbox-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mbox: mailbox@37020000 {
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compatible = "microchip,polarfire-soc-mailbox";
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reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
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interrupt-parent = <&L1>;
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interrupts = <96>;
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#mbox-cells = <1>;
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};
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};

‎Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

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- qcom,ipq6018-apcs-apps-global
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- qcom,ipq8074-apcs-apps-global
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- qcom,msm8916-apcs-kpss-global
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- qcom,msm8939-apcs-kpss-global
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- qcom,msm8994-apcs-kpss-global
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- qcom,msm8996-apcs-hmss-global
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- qcom,msm8998-apcs-hmss-global
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- qcom,sc8180x-apss-shared
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- qcom,sdm660-apcs-hmss-global
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- qcom,sdm845-apss-shared
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- qcom,sm6125-apcs-hmss-global
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- qcom,sm8150-apss-shared
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reg:
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- qcom,sc7180-apss-shared
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- qcom,sdm660-apcs-hmss-global
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- qcom,sdm845-apss-shared
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- qcom,sm6125-apcs-hmss-global
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- qcom,sm8150-apss-shared
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then:
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properties:

‎Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
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maintainers:
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- Conor Dooley <[email protected]>
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description: |
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The PolarFire SoC system controller is communicated with via a mailbox.
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This document describes the bindings for the client portion of that mailbox.
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properties:
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mboxes:
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maxItems: 1
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compatible:
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const: microchip,polarfire-soc-sys-controller
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required:
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- compatible
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- mboxes
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additionalProperties: false
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examples:
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- |
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syscontroller: syscontroller {
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compatible = "microchip,polarfire-soc-sys-controller";
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mboxes = <&mbox 0>;
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};

‎MAINTAINERS

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F: drivers/mailbox/
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F: include/linux/mailbox_client.h
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F: include/linux/mailbox_controller.h
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F: include/dt-bindings/mailbox/
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F: Documentation/devicetree/bindings/mailbox/
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MAILBOX ARM MHUv2
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N: riscv
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K: riscv
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RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
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M: Lewis Hanly <[email protected]>
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L: [email protected]
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S: Supported
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F: drivers/mailbox/mailbox-mpfs.c
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F: drivers/soc/microchip/
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F: include/soc/microchip/mpfs.h
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1573115740
RNBD BLOCK DRIVERS
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M: Md. Haris Iqbal <[email protected]>
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M: Jack Wang <[email protected]>

‎drivers/mailbox/Kconfig

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Test client to help with testing new Controller driver
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implementations.
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config POLARFIRE_SOC_MAILBOX
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tristate "PolarFire SoC (MPFS) Mailbox"
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depends on HAS_IOMEM
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depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
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help
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This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
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To compile this driver as a module, choose M here. the
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module will be called mailbox-mpfs.
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If unsure, say N.
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config QCOM_APCS_IPC
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tristate "Qualcomm APCS IPC driver"
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depends on ARCH_QCOM || COMPILE_TEST

‎drivers/mailbox/Makefile

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obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
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obj-$(CONFIG_POLARFIRE_SOC_MAILBOX) += mailbox-mpfs.o
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obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o

‎drivers/mailbox/arm_mhu.c

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return -ENOMEM;
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mhu->base = devm_ioremap_resource(dev, &adev->res);
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if (IS_ERR(mhu->base)) {
126-
dev_err(dev, "ioremap failed\n");
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if (IS_ERR(mhu->base))
127126
return PTR_ERR(mhu->base);
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}
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130128
for (i = 0; i < MHU_CHANS; i++) {
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mhu->chan[i].con_priv = &mhu->mlink[i];

‎drivers/mailbox/bcm-flexrm-mailbox.c

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mbox->regs = devm_ioremap_resource(&pdev->dev, iomem);
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if (IS_ERR(mbox->regs)) {
15251525
ret = PTR_ERR(mbox->regs);
1526-
dev_err(&pdev->dev, "Failed to remap mailbox regs: %d\n", ret);
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goto fail;
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}
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regs_end = mbox->regs + resource_size(iomem);

‎drivers/mailbox/bcm-pdc-mailbox.c

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pdcs->pdc_reg_vbase = devm_ioremap_resource(&pdev->dev, pdc_regs);
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if (IS_ERR(pdcs->pdc_reg_vbase)) {
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err = PTR_ERR(pdcs->pdc_reg_vbase);
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dev_err(&pdev->dev, "Failed to map registers: %d\n", err);
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goto cleanup_ring_pool;
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}
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