|
1210 | 1210 | <SYSC_IDLE_SMART>,
|
1211 | 1211 | <SYSC_IDLE_SMART_WKUP>;
|
1212 | 1212 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
1213 |
| - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>, |
1214 |
| - <&timer_sys_clk_div>; |
1215 |
| - clock-names = "fck", "timer_sys_ck"; |
| 1213 | + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; |
| 1214 | + clock-names = "fck"; |
1216 | 1215 | #address-cells = <1>;
|
1217 | 1216 | #size-cells = <1>;
|
1218 | 1217 | ranges = <0x0 0x36000 0x1000>;
|
|
3355 | 3354 | <SYSC_IDLE_SMART>,
|
3356 | 3355 | <SYSC_IDLE_SMART_WKUP>;
|
3357 | 3356 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
3358 |
| - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>, <&timer_sys_clk_div>; |
3359 |
| - clock-names = "fck", "timer_sys_ck"; |
| 3357 | + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; |
| 3358 | + clock-names = "fck"; |
3360 | 3359 | #address-cells = <1>;
|
3361 | 3360 | #size-cells = <1>;
|
3362 | 3361 | ranges = <0x0 0x20000 0x1000>;
|
3363 | 3362 |
|
3364 | 3363 | timer5: timer@0 {
|
3365 | 3364 | compatible = "ti,omap5430-timer";
|
3366 | 3365 | reg = <0x0 0x80>;
|
3367 |
| - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; |
3368 |
| - clock-names = "fck"; |
| 3366 | + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; |
| 3367 | + clock-names = "fck", "timer_sys_ck"; |
3369 | 3368 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
3370 | 3369 | };
|
3371 | 3370 | };
|
|
3382 | 3381 | <SYSC_IDLE_SMART>,
|
3383 | 3382 | <SYSC_IDLE_SMART_WKUP>;
|
3384 | 3383 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
3385 |
| - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>, |
3386 |
| - <&timer_sys_clk_div>; |
3387 |
| - clock-names = "fck", "timer_sys_ck"; |
| 3384 | + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; |
| 3385 | + clock-names = "fck"; |
3388 | 3386 | #address-cells = <1>;
|
3389 | 3387 | #size-cells = <1>;
|
3390 | 3388 | ranges = <0x0 0x22000 0x1000>;
|
3391 | 3389 |
|
3392 | 3390 | timer6: timer@0 {
|
3393 | 3391 | compatible = "ti,omap5430-timer";
|
3394 | 3392 | reg = <0x0 0x80>;
|
3395 |
| - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; |
3396 |
| - clock-names = "fck"; |
| 3393 | + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; |
| 3394 | + clock-names = "fck", "timer_sys_ck"; |
3397 | 3395 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
3398 | 3396 | };
|
3399 | 3397 | };
|
|
3501 | 3499 | timer14: timer@0 {
|
3502 | 3500 | compatible = "ti,omap5430-timer";
|
3503 | 3501 | reg = <0x0 0x80>;
|
3504 |
| - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; |
3505 |
| - clock-names = "fck"; |
| 3502 | + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; |
| 3503 | + clock-names = "fck", "timer_sys_ck"; |
3506 | 3504 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
|
3507 | 3505 | ti,timer-pwm;
|
3508 | 3506 | };
|
|
3529 | 3527 | timer15: timer@0 {
|
3530 | 3528 | compatible = "ti,omap5430-timer";
|
3531 | 3529 | reg = <0x0 0x80>;
|
3532 |
| - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; |
3533 |
| - clock-names = "fck"; |
| 3530 | + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; |
| 3531 | + clock-names = "fck", "timer_sys_ck"; |
3534 | 3532 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
3535 | 3533 | ti,timer-pwm;
|
3536 | 3534 | };
|
|
3557 | 3555 | timer16: timer@0 {
|
3558 | 3556 | compatible = "ti,omap5430-timer";
|
3559 | 3557 | reg = <0x0 0x80>;
|
3560 |
| - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; |
3561 |
| - clock-names = "fck"; |
| 3558 | + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; |
| 3559 | + clock-names = "fck", "timer_sys_ck"; |
3562 | 3560 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
|
3563 | 3561 | ti,timer-pwm;
|
3564 | 3562 | };
|
|
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