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100 | 100 | #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
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101 | 101 | #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
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102 | 102 |
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| 103 | +/* NOTE: Must be equal to the last clock ID increased by one */ |
| 104 | +#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1) |
| 105 | +#define CLKS_NR_DMC (CLK_DIV_DMCD + 1) |
| 106 | +#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1) |
| 107 | + |
103 | 108 | static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
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104 | 109 | SRC_LEFTBUS,
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105 | 110 | DIV_LEFTBUS,
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@@ -807,7 +812,7 @@ static const struct samsung_cmu_info cmu_info __initconst = {
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807 | 812 | .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
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808 | 813 | .cpu_clks = exynos3250_cpu_clks,
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809 | 814 | .nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
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810 |
| - .nr_clk_ids = CLK_NR_CLKS, |
| 815 | + .nr_clk_ids = CLKS_NR_MAIN, |
811 | 816 | .clk_regs = exynos3250_cmu_clk_regs,
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812 | 817 | .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
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813 | 818 | };
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@@ -923,7 +928,7 @@ static const struct samsung_cmu_info dmc_cmu_info __initconst = {
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923 | 928 | .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
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924 | 929 | .div_clks = dmc_div_clks,
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925 | 930 | .nr_div_clks = ARRAY_SIZE(dmc_div_clks),
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926 |
| - .nr_clk_ids = NR_CLKS_DMC, |
| 931 | + .nr_clk_ids = CLKS_NR_DMC, |
927 | 932 | .clk_regs = exynos3250_cmu_dmc_clk_regs,
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928 | 933 | .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
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929 | 934 | };
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@@ -1067,7 +1072,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
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1067 | 1072 | .nr_div_clks = ARRAY_SIZE(isp_div_clks),
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1068 | 1073 | .gate_clks = isp_gate_clks,
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1069 | 1074 | .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
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1070 |
| - .nr_clk_ids = NR_CLKS_ISP, |
| 1075 | + .nr_clk_ids = CLKS_NR_ISP, |
1071 | 1076 | };
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1072 | 1077 |
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1073 | 1078 | static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
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