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Marc Zyngierdlezcano
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clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming
Switching from TVAL to CVAL has a small drawback: we need an ISB before reading the counter. We cannot get rid of it, but we can instead remove the one that comes just after writing to CVAL. This reduces the number of ISBs from 3 to 2 when programming the timer. Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Daniel Lezcano <[email protected]>
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-4
lines changed

2 files changed

+4
-4
lines changed

arch/arm/include/asm/arch_timer.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
3131
switch (reg) {
3232
case ARCH_TIMER_REG_CTRL:
3333
asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
34+
isb();
3435
break;
3536
case ARCH_TIMER_REG_CVAL:
3637
asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
@@ -42,6 +43,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
4243
switch (reg) {
4344
case ARCH_TIMER_REG_CTRL:
4445
asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
46+
isb();
4547
break;
4648
case ARCH_TIMER_REG_CVAL:
4749
asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val));
@@ -52,8 +54,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
5254
} else {
5355
BUILD_BUG();
5456
}
55-
56-
isb();
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}
5858

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static __always_inline

arch/arm64/include/asm/arch_timer.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -95,6 +95,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
9595
switch (reg) {
9696
case ARCH_TIMER_REG_CTRL:
9797
write_sysreg(val, cntp_ctl_el0);
98+
isb();
9899
break;
99100
case ARCH_TIMER_REG_CVAL:
100101
write_sysreg(val, cntp_cval_el0);
@@ -106,6 +107,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
106107
switch (reg) {
107108
case ARCH_TIMER_REG_CTRL:
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write_sysreg(val, cntv_ctl_el0);
110+
isb();
109111
break;
110112
case ARCH_TIMER_REG_CVAL:
111113
write_sysreg(val, cntv_cval_el0);
@@ -116,8 +118,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
116118
} else {
117119
BUILD_BUG();
118120
}
119-
120-
isb();
121121
}
122122

123123
static __always_inline

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