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Anson-HuangpH5
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dt-bindings: reset: imx7: Add support for i.MX8MN
i.MX8MN can reuse i.MX8MQ's reset driver, update the compatible property and related info to support i.MX8MN. Signed-off-by: Anson Huang <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
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-29
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lines changed

‎Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ Required properties:
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- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
1010
- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
1111
- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"
12+
- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"
1213
- reg: should be register base and length as documented in the
1314
datasheet
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- interrupts: Should contain SRC interrupt
@@ -49,4 +50,5 @@ Example:
4950
For list of all valid reset indices see
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<dt-bindings/reset/imx7-reset.h> for i.MX7,
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
52-
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM
53+
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and
54+
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN

‎include/dt-bindings/reset/imx8mq-reset.h

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -28,36 +28,36 @@
2828
#define IMX8MQ_RESET_A53_L2RESET 17
2929
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
3030
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
31-
#define IMX8MQ_RESET_OTG2_PHY_RESET 20
32-
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
33-
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
34-
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
35-
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
36-
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
37-
#define IMX8MQ_RESET_PCIEPHY 26
38-
#define IMX8MQ_RESET_PCIEPHY_PERST 27
39-
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
40-
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
41-
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
31+
#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
32+
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
33+
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
34+
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
35+
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
36+
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
37+
#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
38+
#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
39+
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
40+
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
41+
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
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#define IMX8MQ_RESET_DISP_RESET 31
4343
#define IMX8MQ_RESET_GPU_RESET 32
44-
#define IMX8MQ_RESET_VPU_RESET 33
45-
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
46-
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
47-
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
48-
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
49-
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
50-
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
51-
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
52-
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
53-
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
54-
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
55-
#define IMX8MQ_RESET_DDRC1_PRST 44
56-
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
57-
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
58-
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
59-
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
60-
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
44+
#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
45+
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
46+
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
47+
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
48+
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
49+
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
50+
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
51+
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
52+
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
53+
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
54+
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
55+
#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
56+
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
57+
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
58+
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
59+
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
60+
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
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6262
#define IMX8MQ_RESET_NUM 50
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