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Ben Skeggs
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drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_curs_set()
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
1 parent dbb23f5 commit ed0b86a

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5 files changed

+60
-27
lines changed

5 files changed

+60
-27
lines changed

‎drivers/gpu/drm/nouveau/dispnv50/head507d.c

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -137,10 +137,16 @@ head507d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
137137
if ((ret = PUSH_WAIT(push, 3)))
138138
return ret;
139139

140-
PUSH_NVSQ(push, NV507D, 0x0880 + (i * 0x400), 0x80000000 |
141-
asyh->curs.layout << 26 |
142-
asyh->curs.format << 24,
143-
0x0884 + (i * 0x400), asyh->curs.offset >> 8);
140+
PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
141+
NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
142+
NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
143+
NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
144+
NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
145+
NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
146+
NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) |
147+
NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE),
148+
149+
HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
144150
return 0;
145151
}
146152

@@ -149,7 +155,7 @@ head507d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw,
149155
struct nv50_head_atom *asyh)
150156
{
151157
switch (asyw->image.format) {
152-
case 0xcf: asyh->curs.format = 1; break;
158+
case 0xcf: asyh->curs.format = NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8; break;
153159
default:
154160
WARN_ON(1);
155161
return -EINVAL;
@@ -162,8 +168,8 @@ head507d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw,
162168
struct nv50_head_atom *asyh)
163169
{
164170
switch (asyw->image.w) {
165-
case 32: asyh->curs.layout = 0; break;
166-
case 64: asyh->curs.layout = 1; break;
171+
case 32: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break;
172+
case 64: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break;
167173
default:
168174
return -EINVAL;
169175
}

‎drivers/gpu/drm/nouveau/dispnv50/head827d.c

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -51,11 +51,18 @@ head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
5151
if ((ret = PUSH_WAIT(push, 5)))
5252
return ret;
5353

54-
PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x80000000 |
55-
asyh->curs.layout << 26 |
56-
asyh->curs.format << 24,
57-
0x0884 + (i * 0x400), asyh->curs.offset >> 8);
58-
PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), asyh->curs.handle);
54+
PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
55+
NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
56+
NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
57+
NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
58+
NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
59+
NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
60+
NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) |
61+
NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE),
62+
63+
HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
64+
65+
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
5966
return 0;
6067
}
6168

‎drivers/gpu/drm/nouveau/dispnv50/head907d.c

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -166,11 +166,17 @@ head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
166166
if ((ret = PUSH_WAIT(push, 5)))
167167
return ret;
168168

169-
PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x80000000 |
170-
asyh->curs.layout << 26 |
171-
asyh->curs.format << 24,
172-
0x0484 + (i * 0x300), asyh->curs.offset >> 8);
173-
PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), asyh->curs.handle);
169+
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
170+
NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
171+
NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
172+
NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
173+
NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
174+
NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
175+
NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND),
176+
177+
HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
178+
179+
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
174180
return 0;
175181
}
176182

‎drivers/gpu/drm/nouveau/dispnv50/head917d.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@
2424

2525
#include <nvif/push507c.h>
2626

27+
#include <nvhw/class/cl917d.h>
28+
2729
static int
2830
head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
2931
{
@@ -73,10 +75,10 @@ head917d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw,
7375
struct nv50_head_atom *asyh)
7476
{
7577
switch (asyw->state.fb->width) {
76-
case 32: asyh->curs.layout = 0; break;
77-
case 64: asyh->curs.layout = 1; break;
78-
case 128: asyh->curs.layout = 2; break;
79-
case 256: asyh->curs.layout = 3; break;
78+
case 32: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break;
79+
case 64: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break;
80+
case 128: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128; break;
81+
case 256: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256; break;
8082
default:
8183
return -EINVAL;
8284
}

‎drivers/gpu/drm/nouveau/dispnv50/headc37d.c

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -116,12 +116,24 @@ headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
116116
if ((ret = PUSH_WAIT(push, 7)))
117117
return ret;
118118

119-
PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x80000000 |
120-
asyh->curs.layout << 8 |
121-
asyh->curs.format << 0,
122-
0x20a0 + (i * 0x400), 0x000072ff);
123-
PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), asyh->curs.handle);
124-
PUSH_NVSQ(push, NVC37D, 0x2090 + (i * 0x400), asyh->curs.offset >> 8);
119+
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
120+
NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
121+
NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
122+
NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
123+
NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
124+
NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
125+
NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, DE_GAMMA, NONE),
126+
127+
HEAD_SET_CONTROL_CURSOR_COMPOSITION(i),
128+
NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, K1, 0xff) |
129+
NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT,
130+
K1) |
131+
NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT,
132+
NEG_K1_TIMES_SRC) |
133+
NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));
134+
135+
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle);
136+
PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8);
125137
return 0;
126138
}
127139

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