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openrisc: Remove unused IMMU tlb workardound
This looks to be some historical code that was used to convert TLB misses on branches from l.bf, l.jal, l.j etc all to a trampoline using l.jr (jump register). I don't see this being used and I don't know the history of it so remove it. Signed-off-by: Stafford Horne <[email protected]>
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arch/openrisc/kernel/head.S

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Original file line numberDiff line numberDiff line change
@@ -1325,215 +1325,6 @@ i_pte_not_present:
13251325

13261326
/* =================================================[ debugging aids ]=== */
13271327

1328-
.align 64
1329-
_immu_trampoline:
1330-
.space 64
1331-
_immu_trampoline_top:
1332-
1333-
#define TRAMP_SLOT_0 (0x0)
1334-
#define TRAMP_SLOT_1 (0x4)
1335-
#define TRAMP_SLOT_2 (0x8)
1336-
#define TRAMP_SLOT_3 (0xc)
1337-
#define TRAMP_SLOT_4 (0x10)
1338-
#define TRAMP_SLOT_5 (0x14)
1339-
#define TRAMP_FRAME_SIZE (0x18)
1340-
1341-
ENTRY(_immu_trampoline_workaround)
1342-
// r2 EEA
1343-
// r6 is physical EEA
1344-
tophys(r6,r2)
1345-
1346-
LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1347-
tophys (r3,r5) // r3 is trampoline (physical)
1348-
1349-
LOAD_SYMBOL_2_GPR(r4,0x15000000)
1350-
l.sw TRAMP_SLOT_0(r3),r4
1351-
l.sw TRAMP_SLOT_1(r3),r4
1352-
l.sw TRAMP_SLOT_4(r3),r4
1353-
l.sw TRAMP_SLOT_5(r3),r4
1354-
1355-
// EPC = EEA - 0x4
1356-
l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1357-
l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1358-
l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1359-
l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1360-
1361-
l.srli r5,r4,26 // check opcode for write access
1362-
l.sfeqi r5,0 // l.j
1363-
l.bf 0f
1364-
l.sfeqi r5,0x11 // l.jr
1365-
l.bf 1f
1366-
l.sfeqi r5,1 // l.jal
1367-
l.bf 2f
1368-
l.sfeqi r5,0x12 // l.jalr
1369-
l.bf 3f
1370-
l.sfeqi r5,3 // l.bnf
1371-
l.bf 4f
1372-
l.sfeqi r5,4 // l.bf
1373-
l.bf 5f
1374-
99:
1375-
l.nop
1376-
l.j 99b // should never happen
1377-
l.nop 1
1378-
1379-
// r2 is EEA
1380-
// r3 is trampoline address (physical)
1381-
// r4 is instruction
1382-
// r6 is physical(EEA)
1383-
//
1384-
// r5
1385-
1386-
2: // l.jal
1387-
1388-
/* 19 20 aa aa l.movhi r9,0xaaaa
1389-
* a9 29 bb bb l.ori r9,0xbbbb
1390-
*
1391-
* where 0xaaaabbbb is EEA + 0x4 shifted right 2
1392-
*/
1393-
1394-
l.addi r6,r2,0x4 // this is 0xaaaabbbb
1395-
1396-
// l.movhi r9,0xaaaa
1397-
l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1398-
l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1399-
l.srli r5,r6,16
1400-
l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1401-
1402-
// l.ori r9,0xbbbb
1403-
l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1404-
l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1405-
l.andi r5,r6,0xffff
1406-
l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1407-
1408-
/* falthrough, need to set up new jump offset */
1409-
1410-
1411-
0: // l.j
1412-
l.slli r6,r4,6 // original offset shifted left 6 - 2
1413-
// l.srli r6,r6,6 // original offset shifted right 2
1414-
1415-
l.slli r4,r2,4 // old jump position: EEA shifted left 4
1416-
// l.srli r4,r4,6 // old jump position: shifted right 2
1417-
1418-
l.addi r5,r3,0xc // new jump position (physical)
1419-
l.slli r5,r5,4 // new jump position: shifted left 4
1420-
1421-
// calculate new jump offset
1422-
// new_off = old_off + (old_jump - new_jump)
1423-
1424-
l.sub r5,r4,r5 // old_jump - new_jump
1425-
l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1426-
l.srli r5,r5,6 // new offset shifted right 2
1427-
1428-
// r5 is new jump offset
1429-
// l.j has opcode 0x0...
1430-
l.sw TRAMP_SLOT_2(r3),r5 // write it back
1431-
1432-
l.j trampoline_out
1433-
l.nop
1434-
1435-
/* ----------------------------- */
1436-
1437-
3: // l.jalr
1438-
1439-
/* 19 20 aa aa l.movhi r9,0xaaaa
1440-
* a9 29 bb bb l.ori r9,0xbbbb
1441-
*
1442-
* where 0xaaaabbbb is EEA + 0x4 shifted right 2
1443-
*/
1444-
1445-
l.addi r6,r2,0x4 // this is 0xaaaabbbb
1446-
1447-
// l.movhi r9,0xaaaa
1448-
l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1449-
l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1450-
l.srli r5,r6,16
1451-
l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1452-
1453-
// l.ori r9,0xbbbb
1454-
l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1455-
l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1456-
l.andi r5,r6,0xffff
1457-
l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1458-
1459-
l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1460-
l.andi r5,r5,0x3ff // clear out opcode part
1461-
l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1462-
l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1463-
1464-
/* falthrough */
1465-
1466-
1: // l.jr
1467-
l.j trampoline_out
1468-
l.nop
1469-
1470-
/* ----------------------------- */
1471-
1472-
4: // l.bnf
1473-
5: // l.bf
1474-
l.slli r6,r4,6 // original offset shifted left 6 - 2
1475-
// l.srli r6,r6,6 // original offset shifted right 2
1476-
1477-
l.slli r4,r2,4 // old jump position: EEA shifted left 4
1478-
// l.srli r4,r4,6 // old jump position: shifted right 2
1479-
1480-
l.addi r5,r3,0xc // new jump position (physical)
1481-
l.slli r5,r5,4 // new jump position: shifted left 4
1482-
1483-
// calculate new jump offset
1484-
// new_off = old_off + (old_jump - new_jump)
1485-
1486-
l.add r6,r6,r4 // (orig_off + old_jump)
1487-
l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1488-
l.srli r6,r6,6 // new offset shifted right 2
1489-
1490-
// r6 is new jump offset
1491-
l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1492-
l.srli r4,r4,16
1493-
l.andi r4,r4,0xfc00 // get opcode part
1494-
l.slli r4,r4,16
1495-
l.or r6,r4,r6 // l.b(n)f new offset
1496-
l.sw TRAMP_SLOT_2(r3),r6 // write it back
1497-
1498-
/* we need to add l.j to EEA + 0x8 */
1499-
tophys (r4,r2) // may not be needed (due to shifts down_
1500-
l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1501-
// jump position = r5 + 0x8 (0x8 compensated)
1502-
l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1503-
1504-
l.slli r4,r4,4 // the amount of info in imediate of jump
1505-
l.srli r4,r4,6 // jump instruction with offset
1506-
l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1507-
1508-
/* fallthrough */
1509-
1510-
trampoline_out:
1511-
// set up new EPC to point to our trampoline code
1512-
LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1513-
l.mtspr r0,r5,SPR_EPCR_BASE
1514-
1515-
// immu_trampoline is (4x) CACHE_LINE aligned
1516-
// and only 6 instructions long,
1517-
// so we need to invalidate only 2 lines
1518-
1519-
/* Establish cache block size
1520-
If BS=0, 16;
1521-
If BS=1, 32;
1522-
r14 contain block size
1523-
*/
1524-
l.mfspr r21,r0,SPR_ICCFGR
1525-
l.andi r21,r21,SPR_ICCFGR_CBS
1526-
l.srli r21,r21,7
1527-
l.ori r23,r0,16
1528-
l.sll r14,r23,r21
1529-
1530-
l.mtspr r0,r5,SPR_ICBIR
1531-
l.add r5,r5,r14
1532-
l.mtspr r0,r5,SPR_ICBIR
1533-
1534-
l.jr r9
1535-
l.nop
1536-
15371328
/*
15381329
* DESC: Prints ASCII character stored in r7
15391330
*

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