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68 | 68 | BYTE_SWAP_GBR = 3,
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69 | 69 | BYTE_SWAP_BRG = 4,
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70 | 70 | BYTE_SWAP_BGR = 5,
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71 |
| - BYTE_SWAP_MAX = 6, |
72 | 71 | };
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73 | 72 |
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74 | 73 | /* Page 0, Register 0x19 */
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@@ -356,8 +355,6 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
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356 | 355 | int hsynclen = mode->hsync_end - mode->hsync_start;
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357 | 356 | int vbporch = mode->vsync_start - mode->vdisplay;
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358 | 357 | int vsynclen = mode->vsync_end - mode->vsync_start;
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359 |
| - u8 byte_swap; |
360 |
| - int ret; |
361 | 358 |
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362 | 359 | /*
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363 | 360 | * Page 4
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@@ -401,16 +398,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
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401 | 398 | regmap_write(priv->regmap, 0x15, vbporch);
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402 | 399 | regmap_write(priv->regmap, 0x16, vsynclen);
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403 | 400 |
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404 |
| - /* Input color swap. Byte order is optional and will default to |
405 |
| - * BYTE_SWAP_BGR to preserve backwards compatibility with existing |
406 |
| - * driver. |
407 |
| - */ |
408 |
| - ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap", |
409 |
| - &byte_swap); |
410 |
| - if (!ret && byte_swap < BYTE_SWAP_MAX) |
411 |
| - regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap); |
412 |
| - else |
413 |
| - regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); |
| 401 | + /* Input color swap. */ |
| 402 | + regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); |
414 | 403 |
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415 | 404 | /* Input clock and sync polarity. */
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416 | 405 | regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
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