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airliedairlied
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Merge tag 'amd-drm-fixes-6.7-2024-01-04' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amdgpu: - DP MST fix - SMU 13.0.6 fixes - Fix displays on macbooks using vega12 - Fix VSC and colorimetry on DP/eDP Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents faa21f4 + f71cee9 commit ed9895d

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9 files changed

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lines changed

9 files changed

+400
-85
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2188,15 +2188,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
21882188

21892189
adev->firmware.gpu_info_fw = NULL;
21902190

2191-
if (adev->mman.discovery_bin) {
2192-
/*
2193-
* FIXME: The bounding box is still needed by Navi12, so
2194-
* temporarily read it from gpu_info firmware. Should be dropped
2195-
* when DAL no longer needs it.
2196-
*/
2197-
if (adev->asic_type != CHIP_NAVI12)
2198-
return 0;
2199-
}
2191+
if (adev->mman.discovery_bin)
2192+
return 0;
22002193

22012194
switch (adev->asic_type) {
22022195
default:

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6170,8 +6170,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
61706170

61716171
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
61726172
mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6173-
6174-
if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6173+
else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6174+
stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6175+
stream->signal == SIGNAL_TYPE_EDP) {
61756176
//
61766177
// should decide stream support vsc sdp colorimetry capability
61776178
// before building vsc info packet
@@ -6187,8 +6188,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
61876188
if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
61886189
tf = TRANSFER_FUNC_GAMMA_22;
61896190
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6190-
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
61916191

6192+
if (stream->link->psr_settings.psr_feature_enabled)
6193+
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
61926194
}
61936195
finish:
61946196
dc_sink_release(sink);
@@ -6914,8 +6916,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
69146916
if (IS_ERR(mst_state))
69156917
return PTR_ERR(mst_state);
69166918

6917-
if (!mst_state->pbn_div)
6918-
mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6919+
mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
69196920

69206921
if (!state->duplicated) {
69216922
int max_bpc = conn_state->max_requested_bpc;

‎drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

Lines changed: 109 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -440,7 +440,115 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
440440
.use_urgent_burst_bw = 0
441441
};
442442

443-
struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
443+
struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = {
444+
.clock_limits = {
445+
{
446+
.state = 0,
447+
.dcfclk_mhz = 560.0,
448+
.fabricclk_mhz = 560.0,
449+
.dispclk_mhz = 513.0,
450+
.dppclk_mhz = 513.0,
451+
.phyclk_mhz = 540.0,
452+
.socclk_mhz = 560.0,
453+
.dscclk_mhz = 171.0,
454+
.dram_speed_mts = 1069.0,
455+
},
456+
{
457+
.state = 1,
458+
.dcfclk_mhz = 694.0,
459+
.fabricclk_mhz = 694.0,
460+
.dispclk_mhz = 642.0,
461+
.dppclk_mhz = 642.0,
462+
.phyclk_mhz = 600.0,
463+
.socclk_mhz = 694.0,
464+
.dscclk_mhz = 214.0,
465+
.dram_speed_mts = 1324.0,
466+
},
467+
{
468+
.state = 2,
469+
.dcfclk_mhz = 875.0,
470+
.fabricclk_mhz = 875.0,
471+
.dispclk_mhz = 734.0,
472+
.dppclk_mhz = 734.0,
473+
.phyclk_mhz = 810.0,
474+
.socclk_mhz = 875.0,
475+
.dscclk_mhz = 245.0,
476+
.dram_speed_mts = 1670.0,
477+
},
478+
{
479+
.state = 3,
480+
.dcfclk_mhz = 1000.0,
481+
.fabricclk_mhz = 1000.0,
482+
.dispclk_mhz = 1100.0,
483+
.dppclk_mhz = 1100.0,
484+
.phyclk_mhz = 810.0,
485+
.socclk_mhz = 1000.0,
486+
.dscclk_mhz = 367.0,
487+
.dram_speed_mts = 2000.0,
488+
},
489+
{
490+
.state = 4,
491+
.dcfclk_mhz = 1200.0,
492+
.fabricclk_mhz = 1200.0,
493+
.dispclk_mhz = 1284.0,
494+
.dppclk_mhz = 1284.0,
495+
.phyclk_mhz = 810.0,
496+
.socclk_mhz = 1200.0,
497+
.dscclk_mhz = 428.0,
498+
.dram_speed_mts = 2000.0,
499+
},
500+
{
501+
.state = 5,
502+
.dcfclk_mhz = 1200.0,
503+
.fabricclk_mhz = 1200.0,
504+
.dispclk_mhz = 1284.0,
505+
.dppclk_mhz = 1284.0,
506+
.phyclk_mhz = 810.0,
507+
.socclk_mhz = 1200.0,
508+
.dscclk_mhz = 428.0,
509+
.dram_speed_mts = 2000.0,
510+
},
511+
},
512+
513+
.num_states = 5,
514+
.sr_exit_time_us = 1.9,
515+
.sr_enter_plus_exit_time_us = 4.4,
516+
.urgent_latency_us = 3.0,
517+
.urgent_latency_pixel_data_only_us = 4.0,
518+
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
519+
.urgent_latency_vm_data_only_us = 4.0,
520+
.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
521+
.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
522+
.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
523+
.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
524+
.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
525+
.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
526+
.max_avg_sdp_bw_use_normal_percent = 40.0,
527+
.max_avg_dram_bw_use_normal_percent = 40.0,
528+
.writeback_latency_us = 12.0,
529+
.ideal_dram_bw_after_urgent_percent = 40.0,
530+
.max_request_size_bytes = 256,
531+
.dram_channel_width_bytes = 16,
532+
.fabric_datapath_to_dcn_data_return_bytes = 64,
533+
.dcn_downspread_percent = 0.5,
534+
.downspread_percent = 0.5,
535+
.dram_page_open_time_ns = 50.0,
536+
.dram_rw_turnaround_time_ns = 17.5,
537+
.dram_return_buffer_per_channel_bytes = 8192,
538+
.round_trip_ping_latency_dcfclk_cycles = 131,
539+
.urgent_out_of_order_return_per_channel_bytes = 4096,
540+
.channel_interleave_bytes = 256,
541+
.num_banks = 8,
542+
.num_chans = 16,
543+
.vmm_page_size_bytes = 4096,
544+
.dram_clock_change_latency_us = 45.0,
545+
.writeback_dram_clock_change_latency_us = 23.0,
546+
.return_bus_width_bytes = 64,
547+
.dispclk_dppclk_vco_speed_mhz = 3850,
548+
.xfc_bus_transport_time_us = 20,
549+
.xfc_xbuf_latency_tolerance_us = 50,
550+
.use_urgent_burst_bw = 0,
551+
};
444552

445553
struct _vcs_dpi_ip_params_st dcn2_1_ip = {
446554
.odm_capable = 1,

‎drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -147,12 +147,15 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
147147
}
148148

149149
/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */
150-
if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
151-
vsc_packet_revision = vsc_packet_rev4;
152-
else if (stream->link->replay_settings.config.replay_supported)
150+
if (stream->link->psr_settings.psr_feature_enabled) {
151+
if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
152+
vsc_packet_revision = vsc_packet_rev4;
153+
else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
154+
vsc_packet_revision = vsc_packet_rev2;
155+
}
156+
157+
if (stream->link->replay_settings.config.replay_supported)
153158
vsc_packet_revision = vsc_packet_rev4;
154-
else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
155-
vsc_packet_revision = vsc_packet_rev2;
156159

157160
/* Update to revision 5 for extended colorimetry support */
158161
if (stream->use_vsc_sdp_for_colorimetry)

‎drivers/gpu/drm/amd/include/kgd_pp_interface.h

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,7 @@ enum pp_xgmi_plpd_mode {
318318
#define MAX_GFX_CLKS 8
319319
#define MAX_CLKS 4
320320
#define NUM_VCN 4
321+
#define NUM_JPEG_ENG 32
321322

322323
struct seq_file;
323324
enum amd_pp_clock_type;
@@ -774,6 +775,85 @@ struct gpu_metrics_v1_4 {
774775
uint16_t padding;
775776
};
776777

778+
struct gpu_metrics_v1_5 {
779+
struct metrics_table_header common_header;
780+
781+
/* Temperature (Celsius) */
782+
uint16_t temperature_hotspot;
783+
uint16_t temperature_mem;
784+
uint16_t temperature_vrsoc;
785+
786+
/* Power (Watts) */
787+
uint16_t curr_socket_power;
788+
789+
/* Utilization (%) */
790+
uint16_t average_gfx_activity;
791+
uint16_t average_umc_activity; // memory controller
792+
uint16_t vcn_activity[NUM_VCN];
793+
uint16_t jpeg_activity[NUM_JPEG_ENG];
794+
795+
/* Energy (15.259uJ (2^-16) units) */
796+
uint64_t energy_accumulator;
797+
798+
/* Driver attached timestamp (in ns) */
799+
uint64_t system_clock_counter;
800+
801+
/* Throttle status */
802+
uint32_t throttle_status;
803+
804+
/* Clock Lock Status. Each bit corresponds to clock instance */
805+
uint32_t gfxclk_lock_status;
806+
807+
/* Link width (number of lanes) and speed (in 0.1 GT/s) */
808+
uint16_t pcie_link_width;
809+
uint16_t pcie_link_speed;
810+
811+
/* XGMI bus width and bitrate (in Gbps) */
812+
uint16_t xgmi_link_width;
813+
uint16_t xgmi_link_speed;
814+
815+
/* Utilization Accumulated (%) */
816+
uint32_t gfx_activity_acc;
817+
uint32_t mem_activity_acc;
818+
819+
/*PCIE accumulated bandwidth (GB/sec) */
820+
uint64_t pcie_bandwidth_acc;
821+
822+
/*PCIE instantaneous bandwidth (GB/sec) */
823+
uint64_t pcie_bandwidth_inst;
824+
825+
/* PCIE L0 to recovery state transition accumulated count */
826+
uint64_t pcie_l0_to_recov_count_acc;
827+
828+
/* PCIE replay accumulated count */
829+
uint64_t pcie_replay_count_acc;
830+
831+
/* PCIE replay rollover accumulated count */
832+
uint64_t pcie_replay_rover_count_acc;
833+
834+
/* PCIE NAK sent accumulated count */
835+
uint32_t pcie_nak_sent_count_acc;
836+
837+
/* PCIE NAK received accumulated count */
838+
uint32_t pcie_nak_rcvd_count_acc;
839+
840+
/* XGMI accumulated data transfer size(KiloBytes) */
841+
uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
842+
uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
843+
844+
/* PMFW attached timestamp (10ns resolution) */
845+
uint64_t firmware_timestamp;
846+
847+
/* Current clocks (Mhz) */
848+
uint16_t current_gfxclk[MAX_GFX_CLKS];
849+
uint16_t current_socclk[MAX_CLKS];
850+
uint16_t current_vclk0[MAX_CLKS];
851+
uint16_t current_dclk0[MAX_CLKS];
852+
uint16_t current_uclk;
853+
854+
uint16_t padding;
855+
};
856+
777857
/*
778858
* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
779859
* Use gpu_metrics_v2_1 or later instead.

‎drivers/gpu/drm/amd/pm/amdgpu_pm.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2128,7 +2128,9 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
21282128
if (amdgpu_dpm_is_overdrive_supported(adev))
21292129
*states = ATTR_STATE_SUPPORTED;
21302130
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2131-
if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2131+
if ((adev->flags & AMD_IS_APU &&
2132+
gc_ver != IP_VERSION(9, 4, 3)) ||
2133+
gc_ver == IP_VERSION(9, 0, 1))
21322134
*states = ATTR_STATE_UNSUPPORTED;
21332135
} else if (DEVICE_ATTR_IS(pcie_bw)) {
21342136
/* PCIe Perf counters won't work on APU nodes */

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