Skip to content

Commit ee3c3e3

Browse files
vsyrjalavsyrjala
committed
drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c
Now that all pre-skl platforms have their own .min_alignment() functions the remainder of intel_surf_alignment() can be hoisted into skl_univerals_plane.c (and renamed appropriately). Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
1 parent e1488b7 commit ee3c3e3

File tree

3 files changed

+78
-80
lines changed

3 files changed

+78
-80
lines changed

‎drivers/gpu/drm/i915/display/intel_fb.c

Lines changed: 1 addition & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -585,7 +585,7 @@ static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_pl
585585
return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
586586
}
587587

588-
static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
588+
bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
589589
{
590590
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
591591
color_plane == 1;
@@ -777,81 +777,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
777777
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
778778
}
779779

780-
unsigned int intel_surf_alignment(struct intel_plane *plane,
781-
const struct drm_framebuffer *fb,
782-
int color_plane)
783-
{
784-
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
785-
786-
if (intel_fb_uses_dpt(fb)) {
787-
/* AUX_DIST needs only 4K alignment */
788-
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
789-
return 512 * 4096;
790-
791-
/*
792-
* FIXME ADL sees GGTT/DMAR faults with async
793-
* flips unless we align to 16k at least.
794-
* Figure out what's going on here...
795-
*/
796-
if (IS_ALDERLAKE_P(dev_priv) &&
797-
!intel_fb_is_ccs_modifier(fb->modifier) &&
798-
HAS_ASYNC_FLIPS(dev_priv))
799-
return 512 * 16 * 1024;
800-
801-
return 512 * 4096;
802-
}
803-
804-
/* AUX_DIST needs only 4K alignment */
805-
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
806-
return 4096;
807-
808-
if (is_semiplanar_uv_plane(fb, color_plane)) {
809-
/*
810-
* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
811-
* alignment for linear UV planes on all platforms.
812-
*/
813-
if (DISPLAY_VER(dev_priv) >= 12) {
814-
if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
815-
return 256 * 1024;
816-
817-
return intel_tile_row_size(fb, color_plane);
818-
}
819-
820-
return 4096;
821-
}
822-
823-
drm_WARN_ON(&dev_priv->drm, color_plane != 0);
824-
825-
switch (fb->modifier) {
826-
case DRM_FORMAT_MOD_LINEAR:
827-
return 256 * 1024;
828-
case I915_FORMAT_MOD_X_TILED:
829-
if (HAS_ASYNC_FLIPS(dev_priv))
830-
return 256 * 1024;
831-
return 0;
832-
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
833-
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
834-
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
835-
case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
836-
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
837-
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
838-
return 16 * 1024;
839-
case I915_FORMAT_MOD_Y_TILED_CCS:
840-
case I915_FORMAT_MOD_Yf_TILED_CCS:
841-
case I915_FORMAT_MOD_Y_TILED:
842-
case I915_FORMAT_MOD_4_TILED:
843-
case I915_FORMAT_MOD_Yf_TILED:
844-
return 1 * 1024 * 1024;
845-
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
846-
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
847-
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
848-
return 16 * 1024;
849-
default:
850-
MISSING_CASE(fb->modifier);
851-
return 0;
852-
}
853-
}
854-
855780
void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
856781
const struct drm_framebuffer *fb,
857782
int color_plane)

‎drivers/gpu/drm/i915/display/intel_fb.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
3434
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
3535
bool intel_fb_is_mc_ccs_modifier(u64 modifier);
3636

37+
bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
3738
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
3839
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
3940

@@ -60,9 +61,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane
6061
unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane);
6162
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
6263
int color_plane, unsigned int height);
63-
unsigned int intel_surf_alignment(struct intel_plane *plane,
64-
const struct drm_framebuffer *fb,
65-
int color_plane);
6664

6765
void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
6866
const struct drm_framebuffer *fb,

‎drivers/gpu/drm/i915/display/skl_universal_plane.c

Lines changed: 76 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -503,6 +503,81 @@ skl_plane_max_stride(struct intel_plane *plane,
503503
max_pixels, max_bytes);
504504
}
505505

506+
static unsigned int skl_plane_min_alignment(struct intel_plane *plane,
507+
const struct drm_framebuffer *fb,
508+
int color_plane)
509+
{
510+
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
511+
512+
if (intel_fb_uses_dpt(fb)) {
513+
/* AUX_DIST needs only 4K alignment */
514+
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
515+
return 512 * 4096;
516+
517+
/*
518+
* FIXME ADL sees GGTT/DMAR faults with async
519+
* flips unless we align to 16k at least.
520+
* Figure out what's going on here...
521+
*/
522+
if (IS_ALDERLAKE_P(dev_priv) &&
523+
!intel_fb_is_ccs_modifier(fb->modifier) &&
524+
HAS_ASYNC_FLIPS(dev_priv))
525+
return 512 * 16 * 1024;
526+
527+
return 512 * 4096;
528+
}
529+
530+
/* AUX_DIST needs only 4K alignment */
531+
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
532+
return 4096;
533+
534+
if (is_semiplanar_uv_plane(fb, color_plane)) {
535+
/*
536+
* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
537+
* alignment for linear UV planes on all platforms.
538+
*/
539+
if (DISPLAY_VER(dev_priv) >= 12) {
540+
if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
541+
return 256 * 1024;
542+
543+
return intel_tile_row_size(fb, color_plane);
544+
}
545+
546+
return 4096;
547+
}
548+
549+
drm_WARN_ON(&dev_priv->drm, color_plane != 0);
550+
551+
switch (fb->modifier) {
552+
case DRM_FORMAT_MOD_LINEAR:
553+
return 256 * 1024;
554+
case I915_FORMAT_MOD_X_TILED:
555+
if (HAS_ASYNC_FLIPS(dev_priv))
556+
return 256 * 1024;
557+
return 0;
558+
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
559+
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
560+
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
561+
case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
562+
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
563+
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
564+
return 16 * 1024;
565+
case I915_FORMAT_MOD_Y_TILED_CCS:
566+
case I915_FORMAT_MOD_Yf_TILED_CCS:
567+
case I915_FORMAT_MOD_Y_TILED:
568+
case I915_FORMAT_MOD_4_TILED:
569+
case I915_FORMAT_MOD_Yf_TILED:
570+
return 1 * 1024 * 1024;
571+
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
572+
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
573+
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
574+
return 16 * 1024;
575+
default:
576+
MISSING_CASE(fb->modifier);
577+
return 0;
578+
}
579+
}
580+
506581
/* Preoffset values for YUV to RGB Conversion */
507582
#define PREOFF_YUV_TO_RGB_HI 0x1800
508583
#define PREOFF_YUV_TO_RGB_ME 0x0000
@@ -2431,7 +2506,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
24312506
else
24322507
plane->max_stride = skl_plane_max_stride;
24332508

2434-
plane->min_alignment = intel_surf_alignment;
2509+
plane->min_alignment = skl_plane_min_alignment;
24352510

24362511
if (DISPLAY_VER(dev_priv) >= 11) {
24372512
plane->update_noarm = icl_plane_update_noarm;

0 commit comments

Comments
 (0)