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Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late
RISC-V Devicetrees for v6.9 Microchip: Missing bus clocks for the CAN controllers spotted during the creation of a driver for the controllers and a specific compatible for the SiFive PDMA block on PolarFire SoC. Starfive: PWM nodes for the jh7100 and jh7110. Camera subsystem support for the latter. Most notably however is the addition of ethernet support for the jh7110 which finally allows people to use the network on the OG VisionFive and on the Beagle-V Starlight board. This was made possible by the non-standard cache management operations support added for the RZ/Five which could be extended to the ccache present on the jh7100. bindings: Additional clarification for what the reg property represents for cpus and two opencores PWM binding changes - the original addition and an added compatible. The latter is here as the driver patch was not ready but the PWM maintainer told me to go ahead and merge it. Signed-off-by: Conor Dooley <[email protected]> * tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110: Add camera subsystem nodes dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio riscv: dts: starfive: visionfive-v1: Setup ethernet phy riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes riscv: dts: starfive: jh7110: Add PWM node and pins configuration riscv: dts: starfive: jh7100: Add PWM node and pins configuration dt-bindings: pwm: Add bindings for OpenCores PWM Controller Link: https://lore.kernel.org/r/20240305-iodine-moneywise-53797ae9bf6e@spud Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/pwm/opencores,pwm.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: OpenCores PWM controller
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maintainers:
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- William Qiu <[email protected]>
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description:
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The OpenCores PTC ip core contains a PWM controller. When operating in PWM
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mode, the PTC core generates binary signal with user-programmable low and
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high periods. All PTC counters and registers are 32-bit.
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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items:
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- enum:
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- starfive,jh7100-pwm
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- starfive,jh7110-pwm
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- starfive,jh8100-pwm
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- const: opencores,pwm-v1
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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"#pwm-cells":
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const: 3
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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pwm@12490000 {
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compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
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reg = <0x12490000 0x10000>;
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clocks = <&clkgen 181>;
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resets = <&rstgen 109>;
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#pwm-cells = <3>;
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};

‎Documentation/devicetree/bindings/riscv/cpus.yaml

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@@ -75,6 +75,10 @@ properties:
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- riscv,sv57
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- riscv,none
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reg:
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description:
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The hart ID of this CPU node.
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riscv,cbom-block-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:

‎arch/riscv/boot/dts/microchip/mpfs.dtsi

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};
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pdma: dma-controller@3000000 {
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compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
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compatible = "microchip,mpfs-pdma", "sifive,pdma0";
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reg = <0x0 0x3000000 0x0 0x8000>;
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interrupt-parent = <&plic>;
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interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
@@ -422,7 +422,7 @@
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can0: can@2010c000 {
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compatible = "microchip,mpfs-can";
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reg = <0x0 0x2010c000 0x0 0x1000>;
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clocks = <&clkcfg CLK_CAN0>;
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clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
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interrupt-parent = <&plic>;
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interrupts = <56>;
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status = "disabled";
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can1: can@2010d000 {
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compatible = "microchip,mpfs-can";
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reg = <0x0 0x2010d000 0x0 0x1000>;
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clocks = <&clkcfg CLK_CAN1>;
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clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
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interrupt-parent = <&plic>;
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interrupts = <57>;
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status = "disabled";

‎arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts

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model = "BeagleV Starlight Beta";
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compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
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};
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&gmac {
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phy-handle = <&phy>;
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};
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&mdio {
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phy: ethernet-phy@7 {
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reg = <7>;
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reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
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};
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};

‎arch/riscv/boot/dts/starfive/jh7100-common.dtsi

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};
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};
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&gmac {
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pinctrl-names = "default";
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pinctrl-0 = <&gmac_pins>;
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phy-mode = "rgmii-id";
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status = "okay";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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};
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&gpio {
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gmac_pins: gmac-0 {
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gtxclk-pins {
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pins = <PAD_FUNC_SHARE(115)>;
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bias-pull-up;
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drive-strength = <35>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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miitxclk-pins {
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pins = <PAD_FUNC_SHARE(116)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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tx-pins {
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pins = <PAD_FUNC_SHARE(117)>,
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<PAD_FUNC_SHARE(119)>,
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<PAD_FUNC_SHARE(120)>,
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<PAD_FUNC_SHARE(121)>,
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<PAD_FUNC_SHARE(122)>,
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<PAD_FUNC_SHARE(123)>,
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<PAD_FUNC_SHARE(124)>,
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<PAD_FUNC_SHARE(125)>,
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<PAD_FUNC_SHARE(126)>;
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bias-pull-up;
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drive-strength = <35>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rxclk-pins {
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pins = <PAD_FUNC_SHARE(127)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <6>;
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};
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rxer-pins {
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pins = <PAD_FUNC_SHARE(129)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pins = <PAD_FUNC_SHARE(128)>,
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<PAD_FUNC_SHARE(130)>,
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<PAD_FUNC_SHARE(131)>,
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<PAD_FUNC_SHARE(132)>,
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<PAD_FUNC_SHARE(133)>,
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<PAD_FUNC_SHARE(134)>,
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<PAD_FUNC_SHARE(135)>,
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<PAD_FUNC_SHARE(136)>,
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<PAD_FUNC_SHARE(137)>,
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<PAD_FUNC_SHARE(138)>,
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<PAD_FUNC_SHARE(139)>,
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<PAD_FUNC_SHARE(140)>,
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<PAD_FUNC_SHARE(141)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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i2c0_pins: i2c0-0 {
77161
i2c-pins {
78162
pinmux = <GPIOMUX(62, GPO_LOW,
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115199
};
116200
};
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pwm_pins: pwm-0 {
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pwm-pins {
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pinmux = <GPIOMUX(7,
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GPO_PWM_PAD_OUT_BIT0,
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GPO_PWM_PAD_OE_N_BIT0,
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GPI_NONE)>,
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<GPIOMUX(5,
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GPO_PWM_PAD_OUT_BIT1,
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GPO_PWM_PAD_OE_N_BIT1,
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GPI_NONE)>;
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bias-disable;
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drive-strength = <35>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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sdio0_pins: sdio0-0 {
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clk-pins {
120222
pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
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257359
clock-frequency = <27000000>;
258360
};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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&sdio0 {
261369
broken-cd;
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bus-width = <4>;

‎arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts

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66

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/dts-v1/;
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#include "jh7100-common.dtsi"
9-
#include <dt-bindings/gpio/gpio.h>
109

1110
/ {
1211
model = "StarFive VisionFive V1";
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1817
priority = <224>;
1918
};
2019
};
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&gmac {
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phy-handle = <&phy>;
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};
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/*
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* The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
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* manual adjustment of the RX internal delay to work properly. The default
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* RX delay provided by the driver (1.95ns) is too high, but applying a 50%
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* reduction seems to mitigate the issue.
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*
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* It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
32+
* which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
33+
* responsible for the misbehaviour, not the GMAC.
34+
*/
35+
&mdio {
36+
phy: ethernet-phy@0 {
37+
reg = <0>;
38+
rx-internal-delay-ps = <900>;
39+
};
40+
};

‎arch/riscv/boot/dts/starfive/jh7100.dtsi

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204204
status = "disabled";
205205
};
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207+
gmac: ethernet@10020000 {
208+
compatible = "starfive,jh7100-dwmac", "snps,dwmac";
209+
reg = <0x0 0x10020000 0x0 0x10000>;
210+
clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
211+
<&clkgen JH7100_CLK_GMAC_AHB>,
212+
<&clkgen JH7100_CLK_GMAC_PTP_REF>,
213+
<&clkgen JH7100_CLK_GMAC_TX_INV>,
214+
<&clkgen JH7100_CLK_GMAC_GTX>;
215+
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
216+
resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
217+
reset-names = "ahb";
218+
interrupts = <6>, <7>;
219+
interrupt-names = "macirq", "eth_wake_irq";
220+
max-frame-size = <9000>;
221+
snps,multicast-filter-bins = <32>;
222+
snps,perfect-filter-entries = <128>;
223+
starfive,syscon = <&sysmain 0x70 0>;
224+
rx-fifo-depth = <32768>;
225+
tx-fifo-depth = <16384>;
226+
snps,axi-config = <&stmmac_axi_setup>;
227+
snps,fixed-burst;
228+
snps,force_thresh_dma_mode;
229+
status = "disabled";
230+
231+
stmmac_axi_setup: stmmac-axi-config {
232+
snps,wr_osr_lmt = <16>;
233+
snps,rd_osr_lmt = <16>;
234+
snps,blen = <256 128 64 32 0 0 0>;
235+
};
236+
};
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207238
clkgen: clock-controller@11800000 {
208239
compatible = "starfive,jh7100-clkgen";
209240
reg = <0x0 0x11800000 0x0 0x10000>;
@@ -218,6 +249,11 @@
218249
#reset-cells = <1>;
219250
};
220251

252+
sysmain: syscon@11850000 {
253+
compatible = "starfive,jh7100-sysmain", "syscon";
254+
reg = <0x0 0x11850000 0x0 0x10000>;
255+
};
256+
221257
i2c0: i2c@118b0000 {
222258
compatible = "snps,designware-i2c";
223259
reg = <0x0 0x118b0000 0x0 0x10000>;
@@ -320,6 +356,15 @@
320356
<&rstgen JH7100_RSTN_WDT>;
321357
};
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359+
pwm: pwm@12490000 {
360+
compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
361+
reg = <0x0 0x12490000 0x0 0x10000>;
362+
clocks = <&clkgen JH7100_CLK_PWM_APB>;
363+
resets = <&rstgen JH7100_RSTN_PWM_APB>;
364+
#pwm-cells = <3>;
365+
status = "disabled";
366+
};
367+
323368
sfctemp: temperature-sensor@124a0000 {
324369
compatible = "starfive,jh7100-temp";
325370
reg = <0x0 0x124a0000 0x0 0x10000>;

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