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123 | 123 |
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124 | 124 | /* ELBI registers */
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125 | 125 | #define ELBI_SYS_STTS 0x08
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| 126 | +#define ELBI_CS2_ENABLE 0xa4 |
126 | 127 |
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127 | 128 | /* DBI registers */
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128 | 129 | #define DBI_CON_STATUS 0x44
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@@ -263,6 +264,21 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
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263 | 264 | disable_irq(pcie_ep->perst_irq);
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264 | 265 | }
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265 | 266 |
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| 267 | +static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, |
| 268 | + u32 reg, size_t size, u32 val) |
| 269 | +{ |
| 270 | + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); |
| 271 | + int ret; |
| 272 | + |
| 273 | + writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE); |
| 274 | + |
| 275 | + ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); |
| 276 | + if (ret) |
| 277 | + dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret); |
| 278 | + |
| 279 | + writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE); |
| 280 | +} |
| 281 | + |
266 | 282 | static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
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267 | 283 | {
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268 | 284 | struct dw_pcie *pci = &pcie_ep->pci;
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@@ -519,6 +535,7 @@ static const struct dw_pcie_ops pci_ops = {
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519 | 535 | .link_up = qcom_pcie_dw_link_up,
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520 | 536 | .start_link = qcom_pcie_dw_start_link,
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521 | 537 | .stop_link = qcom_pcie_dw_stop_link,
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| 538 | + .write_dbi2 = qcom_pcie_dw_write_dbi2, |
522 | 539 | };
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523 | 540 |
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524 | 541 | static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
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