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pinctrl: samsung: Add exynos8895 SoC pinctrl configuration
Add support for the pin-controller found on the Exynos8895 SoC used in Samsung Galaxy S8 and S8 Plus phones. It has a newly applied pinctrl register layer for FSYS0 with a different bank type offset that consists of the following bit fields: CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 Signed-off-by: Ivaylo Ivanov <[email protected]> Reviewed-by: Sam Protsenko <[email protected]> Acked-by: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

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Original file line numberDiff line numberDiff line change
@@ -58,6 +58,15 @@ static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/*
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* Bank type for non-alive type. Bit fields:
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* CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2
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*/
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static const struct samsung_pin_bank_type exynos8895_bank_type_off = {
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.fld_width = { 4, 1, 2, 3, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
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};
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/* Pad retention control code for accessing PMU regmap */
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static atomic_t exynos_shared_retention_refcnt;
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@@ -866,6 +875,134 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst =
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.num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
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};
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/* pin banks of exynos8895 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = {
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EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c),
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EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24),
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};
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/* pin banks of exynos8895 pin-controller 1 (ABOX) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00),
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EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04),
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EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08),
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};
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/* pin banks of exynos8895 pin-controller 2 (VTS) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00),
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};
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/* pin banks of exynos8895 pin-controller 3 (FSYS0) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00),
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EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04),
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};
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/* pin banks of exynos8895 pin-controller 4 (FSYS1) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00),
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EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04),
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};
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/* pin banks of exynos8895 pin-controller 5 (BUSC) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00),
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};
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/* pin banks of exynos8895 pin-controller 6 (PERIC0) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00),
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EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04),
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EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08),
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EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C),
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EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
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EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14),
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EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18),
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};
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/* pin banks of exynos8895 pin-controller 7 (PERIC1) */
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static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = {
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EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00),
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EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04),
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EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08),
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EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C),
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EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
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EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14),
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EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18),
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EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C),
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EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20),
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EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24),
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EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28),
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EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C),
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EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30),
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EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
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};
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static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = {
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{
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/* pin-controller instance 0 ALIVE data */
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.pin_banks = exynos8895_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks0),
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 1 ABOX data */
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.pin_banks = exynos8895_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks1),
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}, {
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/* pin-controller instance 2 VTS data */
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.pin_banks = exynos8895_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks2),
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.eint_gpio_init = exynos_eint_gpio_init,
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}, {
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/* pin-controller instance 3 FSYS0 data */
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.pin_banks = exynos8895_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 4 FSYS1 data */
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.pin_banks = exynos8895_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks4),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 5 BUSC data */
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.pin_banks = exynos8895_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks5),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 6 PERIC0 data */
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.pin_banks = exynos8895_pin_banks6,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks6),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 7 PERIC1 data */
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.pin_banks = exynos8895_pin_banks7,
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.nr_banks = ARRAY_SIZE(exynos8895_pin_banks7),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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},
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};
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const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = {
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.ctrl = exynos8895_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl),
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};
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/*
8701007
* Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
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* gpio/pin-mux/pinconfig controllers.

‎drivers/pinctrl/samsung/pinctrl-exynos.h

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@@ -141,6 +141,16 @@
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.name = id \
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}
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#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.type = &exynos8895_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
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{ \
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.type = &exynos850_bank_type_off, \

‎drivers/pinctrl/samsung/pinctrl-samsung.c

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@@ -1477,6 +1477,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = &exynos7885_of_data },
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{ .compatible = "samsung,exynos850-pinctrl",
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.data = &exynos850_of_data },
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{ .compatible = "samsung,exynos8895-pinctrl",
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.data = &exynos8895_of_data },
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{ .compatible = "samsung,exynosautov9-pinctrl",
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.data = &exynosautov9_of_data },
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{ .compatible = "samsung,exynosautov920-pinctrl",

‎drivers/pinctrl/samsung/pinctrl-samsung.h

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Original file line numberDiff line numberDiff line change
@@ -384,6 +384,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
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extern const struct samsung_pinctrl_of_match_data fsd_of_data;

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