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18 | 18 | #include "portdrv.h"
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19 | 19 | #include "../pci.h"
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20 | 20 |
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| 21 | +#define PCI_EXP_DPC_CTL_EN_MASK (PCI_EXP_DPC_CTL_EN_FATAL | \ |
| 22 | + PCI_EXP_DPC_CTL_EN_NONFATAL) |
| 23 | + |
21 | 24 | static const char * const rp_pio_error_string[] = {
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22 | 25 | "Configuration Request received UR Completion", /* Bit Position 0 */
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23 | 26 | "Configuration Request received CA Completion", /* Bit Position 1 */
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@@ -369,12 +372,13 @@ static int dpc_probe(struct pcie_device *dev)
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369 | 372 | }
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370 | 373 |
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371 | 374 | pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
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372 |
| - pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); |
373 | 375 |
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374 |
| - ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; |
| 376 | + pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); |
| 377 | + ctl &= ~PCI_EXP_DPC_CTL_EN_MASK; |
| 378 | + ctl |= PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; |
375 | 379 | pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
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376 |
| - pci_info(pdev, "enabled with IRQ %d\n", dev->irq); |
377 | 380 |
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| 381 | + pci_info(pdev, "enabled with IRQ %d\n", dev->irq); |
378 | 382 | pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
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379 | 383 | cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
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380 | 384 | FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
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