|
703 | 703 | };
|
704 | 704 |
|
705 | 705 | u3phy0: usb-phy@11290000 {
|
706 |
| - compatible = "mediatek,mt2712-u3phy"; |
707 |
| - #address-cells = <2>; |
708 |
| - #size-cells = <2>; |
709 |
| - ranges; |
| 706 | + compatible = "mediatek,mt2712-tphy", |
| 707 | + "mediatek,generic-tphy-v2"; |
| 708 | + #address-cells = <1>; |
| 709 | + #size-cells = <1>; |
| 710 | + ranges = <0 0 0x11290000 0x9000>; |
710 | 711 | status = "okay";
|
711 | 712 |
|
712 |
| - u2port0: usb-phy@11290000 { |
713 |
| - reg = <0 0x11290000 0 0x700>; |
| 713 | + u2port0: usb-phy@0 { |
| 714 | + reg = <0x0 0x700>; |
714 | 715 | clocks = <&clk26m>;
|
715 | 716 | clock-names = "ref";
|
716 | 717 | #phy-cells = <1>;
|
717 | 718 | status = "okay";
|
718 | 719 | };
|
719 | 720 |
|
720 |
| - u2port1: usb-phy@11298000 { |
721 |
| - reg = <0 0x11298000 0 0x700>; |
| 721 | + u2port1: usb-phy@8000 { |
| 722 | + reg = <0x8000 0x700>; |
722 | 723 | clocks = <&clk26m>;
|
723 | 724 | clock-names = "ref";
|
724 | 725 | #phy-cells = <1>;
|
725 | 726 | status = "okay";
|
726 | 727 | };
|
727 | 728 |
|
728 |
| - u3port0: usb-phy@11298700 { |
729 |
| - reg = <0 0x11298700 0 0x900>; |
| 729 | + u3port0: usb-phy@8700 { |
| 730 | + reg = <0x8700 0x900>; |
730 | 731 | clocks = <&clk26m>;
|
731 | 732 | clock-names = "ref";
|
732 | 733 | #phy-cells = <1>;
|
|
766 | 767 | };
|
767 | 768 |
|
768 | 769 | u3phy1: usb-phy@112e0000 {
|
769 |
| - compatible = "mediatek,mt2712-u3phy"; |
770 |
| - #address-cells = <2>; |
771 |
| - #size-cells = <2>; |
772 |
| - ranges; |
| 770 | + compatible = "mediatek,mt2712-tphy", |
| 771 | + "mediatek,generic-tphy-v2"; |
| 772 | + #address-cells = <1>; |
| 773 | + #size-cells = <1>; |
| 774 | + ranges = <0 0 0x112e0000 0x9000>; |
773 | 775 | status = "okay";
|
774 | 776 |
|
775 |
| - u2port2: usb-phy@112e0000 { |
776 |
| - reg = <0 0x112e0000 0 0x700>; |
| 777 | + u2port2: usb-phy@0 { |
| 778 | + reg = <0x0 0x700>; |
777 | 779 | clocks = <&clk26m>;
|
778 | 780 | clock-names = "ref";
|
779 | 781 | #phy-cells = <1>;
|
780 | 782 | status = "okay";
|
781 | 783 | };
|
782 | 784 |
|
783 |
| - u2port3: usb-phy@112e8000 { |
784 |
| - reg = <0 0x112e8000 0 0x700>; |
| 785 | + u2port3: usb-phy@8000 { |
| 786 | + reg = <0x8000 0x700>; |
785 | 787 | clocks = <&clk26m>;
|
786 | 788 | clock-names = "ref";
|
787 | 789 | #phy-cells = <1>;
|
788 | 790 | status = "okay";
|
789 | 791 | };
|
790 | 792 |
|
791 |
| - u3port1: usb-phy@112e8700 { |
792 |
| - reg = <0 0x112e8700 0 0x900>; |
| 793 | + u3port1: usb-phy@8700 { |
| 794 | + reg = <0x8700 0x900>; |
793 | 795 | clocks = <&clk26m>;
|
794 | 796 | clock-names = "ref";
|
795 | 797 | #phy-cells = <1>;
|
|
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