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Chunfeng Yunmbgg
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arm64: dts: mt2712: use non-empty ranges for usb-phy
Use non-empty ranges for usb-phy to make the layout of its registers clearer; Replace deprecated compatible by generic Signed-off-by: Chunfeng Yun <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
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arch/arm64/boot/dts/mediatek/mt2712e.dtsi

Lines changed: 22 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -703,30 +703,31 @@
703703
};
704704

705705
u3phy0: usb-phy@11290000 {
706-
compatible = "mediatek,mt2712-u3phy";
707-
#address-cells = <2>;
708-
#size-cells = <2>;
709-
ranges;
706+
compatible = "mediatek,mt2712-tphy",
707+
"mediatek,generic-tphy-v2";
708+
#address-cells = <1>;
709+
#size-cells = <1>;
710+
ranges = <0 0 0x11290000 0x9000>;
710711
status = "okay";
711712

712-
u2port0: usb-phy@11290000 {
713-
reg = <0 0x11290000 0 0x700>;
713+
u2port0: usb-phy@0 {
714+
reg = <0x0 0x700>;
714715
clocks = <&clk26m>;
715716
clock-names = "ref";
716717
#phy-cells = <1>;
717718
status = "okay";
718719
};
719720

720-
u2port1: usb-phy@11298000 {
721-
reg = <0 0x11298000 0 0x700>;
721+
u2port1: usb-phy@8000 {
722+
reg = <0x8000 0x700>;
722723
clocks = <&clk26m>;
723724
clock-names = "ref";
724725
#phy-cells = <1>;
725726
status = "okay";
726727
};
727728

728-
u3port0: usb-phy@11298700 {
729-
reg = <0 0x11298700 0 0x900>;
729+
u3port0: usb-phy@8700 {
730+
reg = <0x8700 0x900>;
730731
clocks = <&clk26m>;
731732
clock-names = "ref";
732733
#phy-cells = <1>;
@@ -766,30 +767,31 @@
766767
};
767768

768769
u3phy1: usb-phy@112e0000 {
769-
compatible = "mediatek,mt2712-u3phy";
770-
#address-cells = <2>;
771-
#size-cells = <2>;
772-
ranges;
770+
compatible = "mediatek,mt2712-tphy",
771+
"mediatek,generic-tphy-v2";
772+
#address-cells = <1>;
773+
#size-cells = <1>;
774+
ranges = <0 0 0x112e0000 0x9000>;
773775
status = "okay";
774776

775-
u2port2: usb-phy@112e0000 {
776-
reg = <0 0x112e0000 0 0x700>;
777+
u2port2: usb-phy@0 {
778+
reg = <0x0 0x700>;
777779
clocks = <&clk26m>;
778780
clock-names = "ref";
779781
#phy-cells = <1>;
780782
status = "okay";
781783
};
782784

783-
u2port3: usb-phy@112e8000 {
784-
reg = <0 0x112e8000 0 0x700>;
785+
u2port3: usb-phy@8000 {
786+
reg = <0x8000 0x700>;
785787
clocks = <&clk26m>;
786788
clock-names = "ref";
787789
#phy-cells = <1>;
788790
status = "okay";
789791
};
790792

791-
u3port1: usb-phy@112e8700 {
792-
reg = <0 0x112e8700 0 0x900>;
793+
u3port1: usb-phy@8700 {
794+
reg = <0x8700 0x900>;
793795
clocks = <&clk26m>;
794796
clock-names = "ref";
795797
#phy-cells = <1>;

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