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CongDanggeertu
CongDang
authored and
geertu
committed
clk: renesas: cpg-mssr: Add support for R-Car V4M
Initial CPG support for the R-Car V4M (R8A779H0). Signed-off-by: Cong Dang <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be
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‎drivers/clk/renesas/Kconfig

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ config CLK_RENESAS
3333
select CLK_R8A779A0 if ARCH_R8A779A0
3434
select CLK_R8A779F0 if ARCH_R8A779F0
3535
select CLK_R8A779G0 if ARCH_R8A779G0
36+
select CLK_R8A779H0 if ARCH_R8A779H0
3637
select CLK_R9A06G032 if ARCH_R9A06G032
3738
select CLK_R9A07G043 if ARCH_R9A07G043
3839
select CLK_R9A07G044 if ARCH_R9A07G044
@@ -165,6 +166,10 @@ config CLK_R8A779G0
165166
bool "R-Car V4H clock support" if COMPILE_TEST
166167
select CLK_RCAR_GEN4_CPG
167168

169+
config CLK_R8A779H0
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bool "R-Car V4M clock support" if COMPILE_TEST
171+
select CLK_RCAR_GEN4_CPG
172+
168173
config CLK_R9A06G032
169174
bool "RZ/N1D clock support" if COMPILE_TEST
170175

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
3131
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
3232
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
33+
obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
3334
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
3435
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
3536
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o

‎drivers/clk/renesas/r8a779h0-cpg-mssr.c

Lines changed: 241 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,241 @@
1+
// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a779h0 Clock Pulse Generator / Module Standby and Software Reset
4+
*
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* Copyright (C) 2023 Renesas Electronics Corp.
6+
*
7+
* Based on r8a779g0-cpg-mssr.c
8+
*/
9+
10+
#include <linux/bitfield.h>
11+
#include <linux/clk.h>
12+
#include <linux/clk-provider.h>
13+
#include <linux/device.h>
14+
#include <linux/err.h>
15+
#include <linux/kernel.h>
16+
#include <linux/soc/renesas/rcar-rst.h>
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18+
#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
19+
20+
#include "renesas-cpg-mssr.h"
21+
#include "rcar-gen4-cpg.h"
22+
23+
enum clk_ids {
24+
/* Core Clock Outputs exported to DT */
25+
LAST_DT_CORE_CLK = R8A779H0_CLK_R,
26+
27+
/* External Input Clocks */
28+
CLK_EXTAL,
29+
CLK_EXTALR,
30+
31+
/* Internal Core Clocks */
32+
CLK_MAIN,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL3,
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CLK_PLL4,
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CLK_PLL5,
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CLK_PLL6,
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CLK_PLL1_DIV2,
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CLK_PLL2_DIV2,
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CLK_PLL3_DIV2,
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CLK_PLL4_DIV2,
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CLK_PLL4_DIV5,
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CLK_PLL5_DIV2,
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CLK_PLL5_DIV4,
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CLK_PLL6_DIV2,
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CLK_S0,
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CLK_S0_VIO,
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CLK_S0_VC,
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CLK_S0_HSC,
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CLK_SASYNCPER,
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CLK_SV_VIP,
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CLK_SV_IR,
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CLK_IMPASRC,
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CLK_IMPBSRC,
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CLK_VIOSRC,
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CLK_VCSRC,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_OCO,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a779h0_core_clks[] = {
67+
/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
70+
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
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DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
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DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
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DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
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DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
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DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
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DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1),
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DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
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DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
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DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
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DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
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DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
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DEF_FIXED(".impasrc", CLK_IMPASRC, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".impbsrc", CLK_IMPBSRC, CLK_PLL1, 4, 1),
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DEF_FIXED(".viosrc", CLK_VIOSRC, CLK_PLL1, 6, 1),
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DEF_FIXED(".vcsrc", CLK_VCSRC, CLK_PLL1, 6, 1),
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DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
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DEF_RATE(".oco", CLK_OCO, 32768),
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/* Core Clock Outputs */
104+
DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0),
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DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8),
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DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32),
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DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40),
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DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1),
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DEF_FIXED("cl16m", R8A779H0_CLK_CL16M, CLK_S0, 48, 1),
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DEF_FIXED("s0d2_rt", R8A779H0_CLK_S0D2_RT, CLK_S0, 2, 1),
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DEF_FIXED("s0d3_rt", R8A779H0_CLK_S0D3_RT, CLK_S0, 3, 1),
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DEF_FIXED("s0d4_rt", R8A779H0_CLK_S0D4_RT, CLK_S0, 4, 1),
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DEF_FIXED("s0d6_rt", R8A779H0_CLK_S0D6_RT, CLK_S0, 6, 1),
116+
DEF_FIXED("cl16m_rt", R8A779H0_CLK_CL16M_RT, CLK_S0, 48, 1),
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DEF_FIXED("s0d2_per", R8A779H0_CLK_S0D2_PER, CLK_S0, 2, 1),
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DEF_FIXED("s0d3_per", R8A779H0_CLK_S0D3_PER, CLK_S0, 3, 1),
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DEF_FIXED("s0d4_per", R8A779H0_CLK_S0D4_PER, CLK_S0, 4, 1),
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DEF_FIXED("s0d6_per", R8A779H0_CLK_S0D6_PER, CLK_S0, 6, 1),
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DEF_FIXED("s0d12_per", R8A779H0_CLK_S0D12_PER, CLK_S0, 12, 1),
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DEF_FIXED("s0d24_per", R8A779H0_CLK_S0D24_PER, CLK_S0, 24, 1),
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DEF_FIXED("cl16m_per", R8A779H0_CLK_CL16M_PER, CLK_S0, 48, 1),
124+
DEF_FIXED("s0d2_mm", R8A779H0_CLK_S0D2_MM, CLK_S0, 2, 1),
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DEF_FIXED("s0d4_mm", R8A779H0_CLK_S0D4_MM, CLK_S0, 4, 1),
126+
DEF_FIXED("cl16m_mm", R8A779H0_CLK_CL16M_MM, CLK_S0, 48, 1),
127+
DEF_FIXED("s0d2_u3dg", R8A779H0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
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DEF_FIXED("s0d4_u3dg", R8A779H0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
129+
DEF_FIXED("s0d1_vio", R8A779H0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
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DEF_FIXED("s0d2_vio", R8A779H0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
131+
DEF_FIXED("s0d4_vio", R8A779H0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
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DEF_FIXED("s0d8_vio", R8A779H0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
133+
DEF_FIXED("s0d1_vc", R8A779H0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
134+
DEF_FIXED("s0d2_vc", R8A779H0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
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DEF_FIXED("s0d4_vc", R8A779H0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
136+
DEF_FIXED("s0d1_hsc", R8A779H0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
137+
DEF_FIXED("s0d2_hsc", R8A779H0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
138+
DEF_FIXED("s0d4_hsc", R8A779H0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
139+
DEF_FIXED("s0d8_hsc", R8A779H0_CLK_S0D8_HSC, CLK_S0_HSC, 8, 1),
140+
DEF_FIXED("cl16m_hsc", R8A779H0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
141+
DEF_FIXED("sasyncrt", R8A779H0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
142+
DEF_FIXED("sasyncperd1", R8A779H0_CLK_SASYNCPERD1, CLK_SASYNCPER, 1, 1),
143+
DEF_FIXED("sasyncperd2", R8A779H0_CLK_SASYNCPERD2, CLK_SASYNCPER, 2, 1),
144+
DEF_FIXED("sasyncperd4", R8A779H0_CLK_SASYNCPERD4, CLK_SASYNCPER, 4, 1),
145+
DEF_FIXED("svd1_vip", R8A779H0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
146+
DEF_FIXED("svd2_vip", R8A779H0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
147+
DEF_FIXED("svd1_ir", R8A779H0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
148+
DEF_FIXED("svd2_ir", R8A779H0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
149+
DEF_FIXED("cbfusa", R8A779H0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
150+
DEF_FIXED("cpex", R8A779H0_CLK_CPEX, CLK_EXTAL, 2, 1),
151+
DEF_FIXED("cp", R8A779H0_CLK_CP, CLK_EXTAL, 2, 1),
152+
DEF_FIXED("impad1", R8A779H0_CLK_IMPAD1, CLK_IMPASRC, 1, 1),
153+
DEF_FIXED("impad4", R8A779H0_CLK_IMPAD4, CLK_IMPASRC, 4, 1),
154+
DEF_FIXED("impb", R8A779H0_CLK_IMPB, CLK_IMPBSRC, 1, 1),
155+
DEF_FIXED("viobusd1", R8A779H0_CLK_VIOBUSD1, CLK_VIOSRC, 1, 1),
156+
DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1),
157+
DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1),
158+
DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1),
159+
DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
160+
DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
161+
DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
162+
DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
163+
DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
164+
165+
DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870),
166+
DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870),
167+
168+
DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
169+
DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC),
170+
171+
DEF_GEN4_OSC("osc", R8A779H0_CLK_OSC, CLK_EXTAL, 8),
172+
DEF_GEN4_MDSEL("r", R8A779H0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
173+
};
174+
175+
static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
176+
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
177+
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
178+
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
179+
DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1),
180+
};
181+
182+
/*
183+
* CPG Clock Data
184+
*/
185+
/*
186+
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
187+
* 14 13 (MHz)
188+
* ------------------------------------------------------------------------
189+
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
190+
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
191+
* 1 0 Prohibited setting
192+
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
193+
*/
194+
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
195+
(((md) & BIT(13)) >> 13))
196+
197+
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
198+
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
199+
{ 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, },
200+
{ 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, },
201+
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
202+
{ 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, },
203+
};
204+
205+
static int __init r8a779h0_cpg_mssr_init(struct device *dev)
206+
{
207+
const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
208+
u32 cpg_mode;
209+
int error;
210+
211+
error = rcar_rst_read_mode_pins(&cpg_mode);
212+
if (error)
213+
return error;
214+
215+
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
216+
if (!cpg_pll_config->extal_div) {
217+
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
218+
return -EINVAL;
219+
}
220+
221+
return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
222+
}
223+
224+
const struct cpg_mssr_info r8a779h0_cpg_mssr_info __initconst = {
225+
/* Core Clocks */
226+
.core_clks = r8a779h0_core_clks,
227+
.num_core_clks = ARRAY_SIZE(r8a779h0_core_clks),
228+
.last_dt_core_clk = LAST_DT_CORE_CLK,
229+
.num_total_core_clks = MOD_CLK_BASE,
230+
231+
/* Module Clocks */
232+
.mod_clks = r8a779h0_mod_clks,
233+
.num_mod_clks = ARRAY_SIZE(r8a779h0_mod_clks),
234+
.num_hw_mod_clks = 30 * 32,
235+
236+
/* Callbacks */
237+
.init = r8a779h0_cpg_mssr_init,
238+
.cpg_clk_register = rcar_gen4_cpg_clk_register,
239+
240+
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
241+
};

‎drivers/clk/renesas/renesas-cpg-mssr.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -871,6 +871,12 @@ static const struct of_device_id cpg_mssr_match[] = {
871871
.compatible = "renesas,r8a779g0-cpg-mssr",
872872
.data = &r8a779g0_cpg_mssr_info,
873873
},
874+
#endif
875+
#ifdef CONFIG_CLK_R8A779H0
876+
{
877+
.compatible = "renesas,r8a779h0-cpg-mssr",
878+
.data = &r8a779h0_cpg_mssr_info,
879+
},
874880
#endif
875881
{ /* sentinel */ }
876882
};

‎drivers/clk/renesas/renesas-cpg-mssr.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -180,6 +180,7 @@ extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
180180
extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
181181
extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
182182
extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
183+
extern const struct cpg_mssr_info r8a779h0_cpg_mssr_info;
183184

184185
void __init cpg_mssr_early_init(struct device_node *np,
185186
const struct cpg_mssr_info *info);

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