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Merge tag 'at91-dt-6.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
Microchip AT91 device tree updates for v6.14 #2 This update includes: - device tree files for the SAMA7D65 SoC and its evaluation board * tag 'at91-dt-6.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: microchip: add support for sama7d65_curiosity board ARM: dts: microchip: add sama7d65 SoC DT Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎arch/arm/boot/dts/microchip/Makefile

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@@ -12,6 +12,7 @@ DTC_FLAGS_at91-sama5d2_xplained := -@
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DTC_FLAGS_at91-sama5d3_eds := -@
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DTC_FLAGS_at91-sama5d3_xplained := -@
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DTC_FLAGS_at91-sama5d4_xplained := -@
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DTC_FLAGS_at91-sama7d65_curiosity := -@
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DTC_FLAGS_at91-sama7g54_curiosity := -@
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DTC_FLAGS_at91-sama7g5ek := -@
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dtb-$(CONFIG_SOC_AT91RM9200) += \
@@ -90,6 +91,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
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at91-sama5d4_xplained.dtb \
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at91-sama5d4ek.dtb \
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at91-vinco.dtb
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dtb-$(CONFIG_SOC_SAMA7D65) += \
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at91-sama7d65_curiosity.dtb
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dtb-$(CONFIG_SOC_SAMA7G5) += \
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at91-sama7g54_curiosity.dtb \
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at91-sama7g5ek.dtb

‎arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* at91-sama7d65_curiosity.dts - Device Tree file for SAMA7D65 Curiosity board
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*
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* Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Romain Sioen <[email protected]>
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*
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*/
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/dts-v1/;
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#include "sama7d65-pinfunc.h"
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#include "sama7d65.dtsi"
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#include <dt-bindings/mfd/atmel-flexcom.h>
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#include <dt-bindings/pinctrl/at91.h>
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/ {
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model = "Microchip SAMA7D65 Curiosity";
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compatible = "microchip,sama7d65-curiosity", "microchip,sama7d65",
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"microchip,sama7d6", "microchip,sama7";
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aliases {
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serial0 = &uart6;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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};
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&flx6 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
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status = "okay";
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};
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&uart6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart6_default>;
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status = "okay";
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};
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&main_xtal {
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clock-frequency = <24000000>;
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};
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&pioa {
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pinctrl_sdmmc1_default: sdmmc1-default {
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cmd-data {
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pinmux = <PIN_PB22__SDMMC1_CMD>,
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<PIN_PB24__SDMMC1_DAT0>,
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<PIN_PB25__SDMMC1_DAT1>,
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<PIN_PB26__SDMMC1_DAT2>,
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<PIN_PB27__SDMMC1_DAT3>;
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slew-rate = <0>;
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bias-disable;
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};
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ck-cd-rstn-vddsel {
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pinmux = <PIN_PB23__SDMMC1_CK>,
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<PIN_PB21__SDMMC1_RSTN>,
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<PIN_PB30__SDMMC1_1V8SEL>,
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<PIN_PB29__SDMMC1_CD>,
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<PIN_PB28__SDMMC1_WP>;
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slew-rate = <0>;
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bias-disable;
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};
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};
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pinctrl_uart6_default: uart6-default {
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pinmux = <PIN_PD18__FLEXCOM6_IO0>,
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<PIN_PD19__FLEXCOM6_IO1>;
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bias-disable;
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};
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};
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&sdmmc1 {
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc1_default>;
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status = "okay";
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};
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&slow_xtal {
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clock-frequency = <32768>;
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};

‎arch/arm/boot/dts/microchip/sama7d65.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC
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*
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* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Ryan Wanner <[email protected]>
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*
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*/
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/mfd/at91-usart.h>
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/ {
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model = "Microchip SAMA7D65 family SoC";
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compatible = "microchip,sama7d65";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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device_type = "cpu";
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clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
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clock-names = "cpu";
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};
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};
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clocks {
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main_xtal: clock-mainxtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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slow_xtal: clock-slowxtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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pioa: pinctrl@e0014000 {
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compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
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reg = <0xe0014000 0x800>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pmc: clock-controller@e0018000 {
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compatible = "microchip,sama7d65-pmc", "syscon";
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reg = <0xe0018000 0x200>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <2>;
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clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
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clock-names = "td_slck", "md_slck", "main_xtal";
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};
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clk32k: clock-controller@e001d500 {
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compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
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reg = <0xe001d500 0x4>;
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clocks = <&slow_xtal>;
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#clock-cells = <1>;
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};
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sdmmc1: mmc@e1208000 {
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compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
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reg = <0xe1208000 0x400>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
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assigned-clock-rates = <200000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
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status = "disabled";
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};
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pit64b0: timer@e1800000 {
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compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
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reg = <0xe1800000 0x100>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
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clock-names = "pclk", "gclk";
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};
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pit64b1: timer@e1804000 {
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compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
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reg = <0xe1804000 0x100>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>;
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clock-names = "pclk", "gclk";
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};
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flx6: flexcom@e2020000 {
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compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
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reg = <0xe2020000 0x200>;
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ranges = <0x0 0xe2020000 0x800>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
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status = "disabled";
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uart6: serial@200 {
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compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
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clock-names = "usart";
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atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
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atmel,fifo-size = <16>;
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status = "disabled";
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};
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};
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gic: interrupt-controller@e8c11000 {
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compatible = "arm,cortex-a7-gic";
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reg = <0xe8c11000 0x1000>,
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<0xe8c12000 0x2000>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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};
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};
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};

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