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Kathiravan Tandersson
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arm64: dts: qcom: ipq5332: add support for the RDP468 variant
Add the initial device tree support for the Reference Design Platform(RDP) 468 based on IPQ5332 family of SoCs. This patch carries the support for Console UART, SPI NOR, eMMC. Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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arch/arm64/boot/dts/qcom/Makefile

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@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* IPQ5332 RDP468 board device tree source
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*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "ipq5332.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
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compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
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aliases {
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serial0 = &blsp1_uart0;
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};
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chosen {
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stdout-path = "serial0";
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};
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};
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&blsp1_uart0 {
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pinctrl-0 = <&serial_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&blsp1_spi0 {
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pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "micron,n25q128a11", "jedec,spi-nor";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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};
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};
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&sdhc {
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bus-width = <4>;
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max-frequency = <192000000>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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&xo_board {
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clock-frequency = <24000000>;
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};
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/* PINCTRL */
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&tlmm {
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sdc_default_state: sdc-default-state {
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clk-pins {
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pins = "gpio13";
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function = "sdc_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio12";
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function = "sdc_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio8", "gpio9", "gpio10", "gpio11";
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function = "sdc_data";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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spi_0_data_clk_pins: spi-0-data-clk-state {
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pins = "gpio14", "gpio15", "gpio16";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-down;
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};
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spi_0_cs_pins: spi-0-cs-state {
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pins = "gpio17";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-up;
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};
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};

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