Skip to content

Commit f372131

Browse files
bebarinobebarino
committed
Merge tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven: - Add USB clocks, resets and power domains on RZ/G3S - Add Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) clocks and resets on RZ/V2H - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints
2 parents b01bf90 + 3aeccbe commit f372131

File tree

5 files changed

+312
-5
lines changed

5 files changed

+312
-5
lines changed

‎Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,16 @@ properties:
3232
reg:
3333
maxItems: 1
3434

35-
clocks: true
35+
clocks:
36+
minItems: 1
37+
maxItems: 3
3638

3739
'#clock-cells':
3840
const: 1
3941

40-
clock-output-names: true
42+
clock-output-names:
43+
minItems: 3
44+
maxItems: 17
4145

4246
renesas,mode:
4347
description: Board-specific settings of the MD_CK* bits on R-Mobile A1

‎drivers/clk/renesas/r9a08g045-cpg.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -208,6 +208,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
208208
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
209209
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
210210
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
211+
DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
212+
DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
213+
DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
214+
DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3),
211215
DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
212216
DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
213217
DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
@@ -233,6 +237,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
233237
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
234238
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
235239
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
240+
DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),
241+
DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),
242+
DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
243+
DEF_RST(R9A08G045_USB_PRESETN, 0x878, 3),
236244
DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
237245
DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
238246
DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
@@ -280,6 +288,15 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
280288
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
281289
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
282290
RZG2L_PD_F_NONE),
291+
DEF_PD("usb0", R9A08G045_PD_USB0,
292+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)),
293+
RZG2L_PD_F_NONE),
294+
DEF_PD("usb1", R9A08G045_PD_USB1,
295+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)),
296+
RZG2L_PD_F_NONE),
297+
DEF_PD("usb-phy", R9A08G045_PD_USB_PHY,
298+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)),
299+
RZG2L_PD_F_NONE),
283300
DEF_PD("eth0", R9A08G045_PD_ETHER0,
284301
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
285302
RZG2L_PD_F_NONE),

‎drivers/clk/renesas/r9a09g057-cpg.c

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,16 +25,31 @@ enum clk_ids {
2525

2626
/* PLL Clocks */
2727
CLK_PLLCM33,
28+
CLK_PLLCLN,
2829
CLK_PLLDTY,
2930
CLK_PLLCA55,
3031

3132
/* Internal Core Clocks */
3233
CLK_PLLCM33_DIV16,
34+
CLK_PLLCLN_DIV2,
35+
CLK_PLLCLN_DIV8,
36+
CLK_PLLCLN_DIV16,
37+
CLK_PLLDTY_ACPU,
38+
CLK_PLLDTY_ACPU_DIV4,
3339

3440
/* Module Clocks */
3541
MOD_CLK_BASE,
3642
};
3743

44+
static const struct clk_div_table dtable_2_64[] = {
45+
{0, 2},
46+
{1, 4},
47+
{2, 8},
48+
{3, 16},
49+
{4, 64},
50+
{0, 0},
51+
};
52+
3853
static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
3954
/* External Clock Inputs */
4055
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -43,23 +58,92 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
4358

4459
/* PLL Clocks */
4560
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
61+
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
4662
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
4763
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
4864

4965
/* Internal Core Clocks */
5066
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
5167

68+
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
69+
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
70+
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
71+
72+
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
73+
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
74+
5275
/* Core Clocks */
5376
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
5477
DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
5578
};
5679

5780
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
81+
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
82+
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
83+
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
84+
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
85+
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
86+
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
87+
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
88+
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
89+
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
90+
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
91+
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
92+
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
93+
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
94+
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),
95+
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),
96+
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),
5897
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
98+
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
99+
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
100+
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
101+
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
102+
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
103+
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
104+
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
105+
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
106+
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
107+
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),
108+
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
109+
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),
110+
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
111+
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),
112+
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),
113+
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),
114+
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
115+
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),
116+
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
117+
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
118+
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
59119
};
60120

61121
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
122+
DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
123+
DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
124+
DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
125+
DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
126+
DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
127+
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
128+
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
129+
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
130+
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
131+
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
132+
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
133+
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
62134
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
135+
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
136+
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
137+
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
138+
DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
139+
DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
140+
DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
141+
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
142+
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
143+
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
144+
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
145+
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
146+
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
63147
};
64148

65149
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {

0 commit comments

Comments
 (0)