@@ -2519,11 +2519,24 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
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return true;
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}
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+ static void
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+ intel_psr_apply_su_area_workarounds (struct intel_crtc_state * crtc_state )
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+ {
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+ struct intel_display * display = to_intel_display (crtc_state );
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+ struct drm_i915_private * i915 = to_i915 (crtc_state -> uapi .crtc -> dev );
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+
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+ /* Wa_14014971492 */
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+ if (!crtc_state -> has_panel_replay &&
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+ ((IS_DISPLAY_VER_STEP (display , IP_VER (14 , 0 ), STEP_A0 , STEP_B0 ) ||
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+ IS_ALDERLAKE_P (i915 ) || IS_TIGERLAKE (i915 ))) &&
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+ crtc_state -> splitter .enable )
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+ crtc_state -> psr2_su_area .y1 = 0 ;
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+ }
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+
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int intel_psr2_sel_fetch_update (struct intel_atomic_state * state ,
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struct intel_crtc * crtc )
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{
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struct intel_display * display = to_intel_display (state );
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- struct drm_i915_private * dev_priv = to_i915 (state -> base .dev );
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struct intel_crtc_state * crtc_state = intel_atomic_get_new_crtc_state (state , crtc );
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struct intel_plane_state * new_plane_state , * old_plane_state ;
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struct intel_plane * plane ;
@@ -2628,12 +2641,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
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if (full_update )
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goto skip_sel_fetch_set_loop ;
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- /* Wa_14014971492 */
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- if (!crtc_state -> has_panel_replay &&
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- ((IS_DISPLAY_VER_STEP (display , IP_VER (14 , 0 ), STEP_A0 , STEP_B0 ) ||
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- IS_ALDERLAKE_P (dev_priv ) || IS_TIGERLAKE (dev_priv ))) &&
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- crtc_state -> splitter .enable )
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- crtc_state -> psr2_su_area .y1 = 0 ;
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+ intel_psr_apply_su_area_workarounds (crtc_state );
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ret = drm_atomic_add_affected_planes (& state -> base , & crtc -> base );
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if (ret )
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