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Ben Skeggsairlied
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drm/nouveau/sec2/tu102-: prepare for GSP-RM
- add (initial) R535 implementation of SEC2, needed for boot Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild

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@@ -4,3 +4,5 @@ nvkm-y += nvkm/engine/sec2/gp102.o
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nvkm-y += nvkm/engine/sec2/gp108.o
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nvkm-y += nvkm/engine/sec2/tu102.o
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nvkm-y += nvkm/engine/sec2/ga102.o
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nvkm-y += nvkm/engine/sec2/r535.o

drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c

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@@ -21,6 +21,7 @@
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*/
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#include "priv.h"
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#include <subdev/acr.h>
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#include <subdev/gsp.h>
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#include <subdev/vfn.h>
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#include <nvfw/flcn.h>
@@ -193,5 +194,10 @@ ga102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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/* TOP info wasn't updated on Turing to reflect the PRI
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* address change for some reason. We override it here.
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*/
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return nvkm_sec2_new_(ga102_sec2_fwif, device, type, inst, 0x840000, psec2);
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const u32 addr = 0x840000;
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if (nvkm_gsp_rm(device->gsp))
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return r535_sec2_new(&ga102_sec2, device, type, inst, addr, psec2);
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return nvkm_sec2_new_(ga102_sec2_fwif, device, type, inst, addr, psec2);
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}

drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h

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@@ -4,6 +4,9 @@
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#include <engine/sec2.h>
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struct nvkm_acr_lsfw;
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int r535_sec2_new(const struct nvkm_sec2_func *,
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struct nvkm_device *, enum nvkm_subdev_type, int, u32 addr, struct nvkm_sec2 **);
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struct nvkm_sec2_func {
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const struct nvkm_falcon_func *flcn;
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u8 unit_unload;
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@@ -0,0 +1,54 @@
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/*
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* Copyright 2023 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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static void *
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r535_sec2_dtor(struct nvkm_engine *engine)
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{
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struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
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nvkm_falcon_dtor(&sec2->falcon);
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return sec2;
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}
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static const struct nvkm_engine_func
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r535_sec2 = {
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.dtor = r535_sec2_dtor,
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};
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int
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r535_sec2_new(const struct nvkm_sec2_func *func, struct nvkm_device *device,
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enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_sec2 **psec2)
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{
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struct nvkm_sec2 *sec2;
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int ret;
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if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL)))
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return -ENOMEM;
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ret = nvkm_engine_ctor(&r535_sec2, device, type, inst, true, &sec2->engine);
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if (ret)
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return ret;
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return nvkm_falcon_ctor(func->flcn, &sec2->engine.subdev, sec2->engine.subdev.name,
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addr, &sec2->falcon);
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}

drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
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*/
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#include "priv.h"
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#include <subdev/acr.h>
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#include <subdev/gsp.h>
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#include <nvfw/sec2.h>
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@@ -82,5 +83,10 @@ tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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/* TOP info wasn't updated on Turing to reflect the PRI
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* address change for some reason. We override it here.
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*/
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return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2);
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const u32 addr = 0x840000;
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if (nvkm_gsp_rm(device->gsp))
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return r535_sec2_new(&tu102_sec2, device, type, inst, addr, psec2);
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return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, addr, psec2);
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}

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