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shenkibebarino
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clk/ast2600: Fix soc revision for AHB
Move the soc revision parsing to the initial probe, saving the driver from parsing the register multiple times. Use this variable to select the correct divisor table for the AHB clock. Before this fix the A2 would have used the A0 table. Fixes: 2d49106 ("clk: ast2600: Fix AHB clock divider for A1") Signed-off-by: Joel Stanley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Andrew Jeffery <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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drivers/clk/clk-ast2600.c

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,8 @@ static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
5151
static struct clk_hw_onecell_data *aspeed_g6_clk_data;
5252

5353
static void __iomem *scu_g6_base;
54+
/* AST2600 revision: A0, A1, A2, etc */
55+
static u8 soc_rev;
5456

5557
/*
5658
* Clocks marked with CLK_IS_CRITICAL:
@@ -191,9 +193,8 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
191193
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
192194
{
193195
unsigned int mult, div;
194-
u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);
195196

196-
if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {
197+
if (soc_rev >= 2) {
197198
if (val & BIT(24)) {
198199
/* Pass through mode */
199200
mult = div = 1;
@@ -707,7 +708,7 @@ static const u32 ast2600_a1_axi_ahb200_tbl[] = {
707708
static void __init aspeed_g6_cc(struct regmap *map)
708709
{
709710
struct clk_hw *hw;
710-
u32 val, div, divbits, chip_id, axi_div, ahb_div;
711+
u32 val, div, divbits, axi_div, ahb_div;
711712

712713
clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
713714

@@ -738,8 +739,7 @@ static void __init aspeed_g6_cc(struct regmap *map)
738739
axi_div = 2;
739740

740741
divbits = (val >> 11) & 0x3;
741-
regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
742-
if (chip_id & BIT(16)) {
742+
if (soc_rev >= 1) {
743743
if (!divbits) {
744744
ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
745745
if (val & BIT(16))
@@ -784,6 +784,8 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
784784
if (!scu_g6_base)
785785
return;
786786

787+
soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16;
788+
787789
aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
788790
ASPEED_G6_NUM_CLKS), GFP_KERNEL);
789791
if (!aspeed_g6_clk_data)

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