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William Zhangffainelli
William Zhang
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arm64: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv8 chip dts files. Signed-off-by: William Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Florian Fainelli <[email protected]>
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14 files changed

+160
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lines changed

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,12 @@
107107
clock-frequency = <50000000>;
108108
clock-output-names = "periph";
109109
};
110+
111+
hsspi_pll: hsspi-pll {
112+
compatible = "fixed-clock";
113+
#clock-cells = <0>;
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clock-frequency = <400000000>;
115+
};
110116
};
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112118
soc {
@@ -531,6 +537,18 @@
531537
#size-cells = <0>;
532538
};
533539

540+
hsspi: spi@1000{
541+
#address-cells = <1>;
542+
#size-cells = <0>;
543+
compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
544+
reg = <0x1000 0x600>;
545+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
546+
clocks = <&hsspi_pll &hsspi_pll>;
547+
clock-names = "hsspi", "pll";
548+
num-cs = <8>;
549+
status = "disabled";
550+
};
551+
534552
nand-controller@1800 {
535553
#address-cells = <1>;
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#size-cells = <0>;

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,13 +79,20 @@
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#clock-cells = <0>;
8080
clock-frequency = <200000000>;
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};
82+
8283
uart_clk: uart-clk {
8384
compatible = "fixed-factor-clock";
8485
#clock-cells = <0>;
8586
clocks = <&periph_clk>;
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clock-div = <4>;
8788
clock-mult = <1>;
8889
};
90+
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hsspi_pll: hsspi-pll {
92+
compatible = "fixed-clock";
93+
#clock-cells = <0>;
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clock-frequency = <200000000>;
95+
};
8996
};
9097

9198
psci {
@@ -117,6 +124,19 @@
117124
#size-cells = <1>;
118125
ranges = <0x0 0x0 0xff800000 0x800000>;
119126

127+
hsspi: spi@1000 {
128+
#address-cells = <1>;
129+
#size-cells = <0>;
130+
compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
131+
reg = <0x1000 0x600>, <0x2610 0x4>;
132+
reg-names = "hsspi", "spim-ctrl";
133+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
134+
clocks = <&hsspi_pll &hsspi_pll>;
135+
clock-names = "hsspi", "pll";
136+
num-cs = <8>;
137+
status = "disabled";
138+
};
139+
120140
uart0: serial@12000 {
121141
compatible = "arm,pl011", "arm,primecell";
122142
reg = <0x12000 0x1000>;

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,13 +60,20 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
63+
6364
uart_clk: uart-clk {
6465
compatible = "fixed-factor-clock";
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#clock-cells = <0>;
6667
clocks = <&periph_clk>;
6768
clock-div = <4>;
6869
clock-mult = <1>;
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};
71+
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hsspi_pll: hsspi-pll {
73+
compatible = "fixed-clock";
74+
#clock-cells = <0>;
75+
clock-frequency = <200000000>;
76+
};
7077
};
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psci {
@@ -99,6 +106,18 @@
99106
#size-cells = <1>;
100107
ranges = <0x0 0x0 0xff800000 0x800000>;
101108

109+
hsspi: spi@1000 {
110+
#address-cells = <1>;
111+
#size-cells = <0>;
112+
compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
113+
reg = <0x1000 0x600>;
114+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
115+
clocks = <&hsspi_pll &hsspi_pll>;
116+
clock-names = "hsspi", "pll";
117+
num-cs = <8>;
118+
status = "disabled";
119+
};
120+
102121
uart0: serial@12000 {
103122
compatible = "arm,pl011", "arm,primecell";
104123
reg = <0x12000 0x1000>;

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,13 +79,20 @@
7979
#clock-cells = <0>;
8080
clock-frequency = <200000000>;
8181
};
82+
8283
uart_clk: uart-clk {
8384
compatible = "fixed-factor-clock";
8485
#clock-cells = <0>;
8586
clocks = <&periph_clk>;
8687
clock-div = <4>;
8788
clock-mult = <1>;
8889
};
90+
91+
hsspi_pll: hsspi-pll {
92+
compatible = "fixed-clock";
93+
#clock-cells = <0>;
94+
clock-frequency = <400000000>;
95+
};
8996
};
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9198
psci {
@@ -117,6 +124,18 @@
117124
#size-cells = <1>;
118125
ranges = <0x0 0x0 0xff800000 0x800000>;
119126

127+
hsspi: spi@1000 {
128+
#address-cells = <1>;
129+
#size-cells = <0>;
130+
compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
131+
reg = <0x1000 0x600>;
132+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
133+
clocks = <&hsspi_pll &hsspi_pll>;
134+
clock-names = "hsspi", "pll";
135+
num-cs = <8>;
136+
status = "disabled";
137+
};
138+
120139
uart0: serial@12000 {
121140
compatible = "arm,pl011", "arm,primecell";
122141
reg = <0x12000 0x1000>;

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,13 +79,20 @@
7979
#clock-cells = <0>;
8080
clock-frequency = <200000000>;
8181
};
82+
8283
uart_clk: uart-clk {
8384
compatible = "fixed-factor-clock";
8485
#clock-cells = <0>;
8586
clocks = <&periph_clk>;
8687
clock-div = <4>;
8788
clock-mult = <1>;
8889
};
90+
91+
hsspi_pll: hsspi-pll {
92+
compatible = "fixed-clock";
93+
#clock-cells = <0>;
94+
clock-frequency = <200000000>;
95+
};
8996
};
9097

9198
psci {
@@ -117,6 +124,19 @@
117124
#size-cells = <1>;
118125
ranges = <0x0 0x0 0xff800000 0x800000>;
119126

127+
hsspi: spi@1000 {
128+
#address-cells = <1>;
129+
#size-cells = <0>;
130+
compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
131+
reg = <0x1000 0x600>, <0x2610 0x4>;
132+
reg-names = "hsspi", "spim-ctrl";
133+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
134+
clocks = <&hsspi_pll &hsspi_pll>;
135+
clock-names = "hsspi", "pll";
136+
num-cs = <8>;
137+
status = "disabled";
138+
};
139+
120140
uart0: serial@12000 {
121141
compatible = "arm,pl011", "arm,primecell";
122142
reg = <0x12000 0x1000>;

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,12 @@
6060
#clock-cells = <0>;
6161
clock-frequency = <200000000>;
6262
};
63+
64+
hsspi_pll: hsspi-pll {
65+
compatible = "fixed-clock";
66+
#clock-cells = <0>;
67+
clock-frequency = <400000000>;
68+
};
6369
};
6470

6571
psci {
@@ -100,5 +106,17 @@
100106
clock-names = "refclk";
101107
status = "disabled";
102108
};
109+
110+
hsspi: spi@1000 {
111+
#address-cells = <1>;
112+
#size-cells = <0>;
113+
compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
114+
reg = <0x1000 0x600>;
115+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116+
clocks = <&hsspi_pll &hsspi_pll>;
117+
clock-names = "hsspi", "pll";
118+
num-cs = <8>;
119+
status = "disabled";
120+
};
103121
};
104122
};

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,12 @@
7878
#clock-cells = <0>;
7979
clock-frequency = <200000000>;
8080
};
81+
82+
hsspi_pll: hsspi-pll {
83+
compatible = "fixed-clock";
84+
#clock-cells = <0>;
85+
clock-frequency = <400000000>;
86+
};
8187
};
8288

8389
psci {
@@ -137,5 +143,17 @@
137143
clock-names = "refclk";
138144
status = "disabled";
139145
};
146+
147+
hsspi: spi@1000 {
148+
#address-cells = <1>;
149+
#size-cells = <0>;
150+
compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
151+
reg = <0x1000 0x600>;
152+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
153+
clocks = <&hsspi_pll &hsspi_pll>;
154+
clock-names = "hsspi", "pll";
155+
num-cs = <8>;
156+
status = "disabled";
157+
};
140158
};
141159
};

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,3 +28,7 @@
2828
&uart0 {
2929
status = "okay";
3030
};
31+
32+
&hsspi {
33+
status = "okay";
34+
};

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,3 +28,7 @@
2828
&uart0 {
2929
status = "okay";
3030
};
31+
32+
&hsspi {
33+
status = "okay";
34+
};

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,3 +28,7 @@
2828
&uart0 {
2929
status = "okay";
3030
};
31+
32+
&hsspi {
33+
status = "okay";
34+
};

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