Skip to content

Commit f661eb5

Browse files
committed
Merge branch 'for-next/misc' into for-next/core
* for-next/misc: arm64: hibernate: Fix warning for cast from restricted gfp_t arm64: esr: Define ESR_ELx_EC_* constants as UL arm64: Constify struct kobj_type arm64: smp: smp_send_stop() and crash_smp_send_stop() should try non-NMI first arm64/sve: Remove unused declaration read_smcr_features() arm64: mm: Remove unused declaration early_io_map() arm64: el2_setup.h: Rename some labels to be more diff-friendly arm64: signal: Fix some under-bracketed UAPI macros arm64/mm: Drop TCR_SMP_FLAGS arm64/mm: Drop PMD_SECT_VALID
2 parents dd22f44 + ecdd16d commit f661eb5

File tree

10 files changed

+157
-126
lines changed

10 files changed

+157
-126
lines changed

arch/arm64/include/asm/el2_setup.h

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -165,42 +165,45 @@
165165
mrs x1, id_aa64dfr0_el1
166166
ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
167167
cmp x1, #3
168-
b.lt .Lset_debug_fgt_\@
168+
b.lt .Lskip_spe_fgt_\@
169169
/* Disable PMSNEVFR_EL1 read and write traps */
170170
orr x0, x0, #(1 << 62)
171171

172-
.Lset_debug_fgt_\@:
172+
.Lskip_spe_fgt_\@:
173173
msr_s SYS_HDFGRTR_EL2, x0
174174
msr_s SYS_HDFGWTR_EL2, x0
175175

176176
mov x0, xzr
177177
mrs x1, id_aa64pfr1_el1
178178
ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
179-
cbz x1, .Lset_pie_fgt_\@
179+
cbz x1, .Lskip_debug_fgt_\@
180180

181181
/* Disable nVHE traps of TPIDR2 and SMPRI */
182182
orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
183183
orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
184184

185-
.Lset_pie_fgt_\@:
185+
.Lskip_debug_fgt_\@:
186186
mrs_s x1, SYS_ID_AA64MMFR3_EL1
187187
ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
188-
cbz x1, .Lset_fgt_\@
188+
cbz x1, .Lskip_pie_fgt_\@
189189

190190
/* Disable trapping of PIR_EL1 / PIRE0_EL1 */
191191
orr x0, x0, #HFGxTR_EL2_nPIR_EL1
192192
orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1
193193

194-
.Lset_fgt_\@:
194+
.Lskip_pie_fgt_\@:
195195
msr_s SYS_HFGRTR_EL2, x0
196196
msr_s SYS_HFGWTR_EL2, x0
197197
msr_s SYS_HFGITR_EL2, xzr
198198

199199
mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
200200
ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
201-
cbz x1, .Lskip_fgt_\@
201+
cbz x1, .Lskip_amu_fgt_\@
202202

203203
msr_s SYS_HAFGRTR_EL2, xzr
204+
205+
.Lskip_amu_fgt_\@:
206+
204207
.Lskip_fgt_\@:
205208
.endm
206209

arch/arm64/include/asm/esr.h

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -10,63 +10,63 @@
1010
#include <asm/memory.h>
1111
#include <asm/sysreg.h>
1212

13-
#define ESR_ELx_EC_UNKNOWN (0x00)
14-
#define ESR_ELx_EC_WFx (0x01)
13+
#define ESR_ELx_EC_UNKNOWN UL(0x00)
14+
#define ESR_ELx_EC_WFx UL(0x01)
1515
/* Unallocated EC: 0x02 */
16-
#define ESR_ELx_EC_CP15_32 (0x03)
17-
#define ESR_ELx_EC_CP15_64 (0x04)
18-
#define ESR_ELx_EC_CP14_MR (0x05)
19-
#define ESR_ELx_EC_CP14_LS (0x06)
20-
#define ESR_ELx_EC_FP_ASIMD (0x07)
21-
#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
22-
#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
16+
#define ESR_ELx_EC_CP15_32 UL(0x03)
17+
#define ESR_ELx_EC_CP15_64 UL(0x04)
18+
#define ESR_ELx_EC_CP14_MR UL(0x05)
19+
#define ESR_ELx_EC_CP14_LS UL(0x06)
20+
#define ESR_ELx_EC_FP_ASIMD UL(0x07)
21+
#define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
22+
#define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */
2323
/* Unallocated EC: 0x0A - 0x0B */
24-
#define ESR_ELx_EC_CP14_64 (0x0C)
25-
#define ESR_ELx_EC_BTI (0x0D)
26-
#define ESR_ELx_EC_ILL (0x0E)
24+
#define ESR_ELx_EC_CP14_64 UL(0x0C)
25+
#define ESR_ELx_EC_BTI UL(0x0D)
26+
#define ESR_ELx_EC_ILL UL(0x0E)
2727
/* Unallocated EC: 0x0F - 0x10 */
28-
#define ESR_ELx_EC_SVC32 (0x11)
29-
#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
30-
#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
28+
#define ESR_ELx_EC_SVC32 UL(0x11)
29+
#define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */
30+
#define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */
3131
/* Unallocated EC: 0x14 */
32-
#define ESR_ELx_EC_SVC64 (0x15)
33-
#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
34-
#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
35-
#define ESR_ELx_EC_SYS64 (0x18)
36-
#define ESR_ELx_EC_SVE (0x19)
37-
#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
32+
#define ESR_ELx_EC_SVC64 UL(0x15)
33+
#define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */
34+
#define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */
35+
#define ESR_ELx_EC_SYS64 UL(0x18)
36+
#define ESR_ELx_EC_SVE UL(0x19)
37+
#define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */
3838
/* Unallocated EC: 0x1B */
39-
#define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */
40-
#define ESR_ELx_EC_SME (0x1D)
39+
#define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */
40+
#define ESR_ELx_EC_SME UL(0x1D)
4141
/* Unallocated EC: 0x1E */
42-
#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
43-
#define ESR_ELx_EC_IABT_LOW (0x20)
44-
#define ESR_ELx_EC_IABT_CUR (0x21)
45-
#define ESR_ELx_EC_PC_ALIGN (0x22)
42+
#define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
43+
#define ESR_ELx_EC_IABT_LOW UL(0x20)
44+
#define ESR_ELx_EC_IABT_CUR UL(0x21)
45+
#define ESR_ELx_EC_PC_ALIGN UL(0x22)
4646
/* Unallocated EC: 0x23 */
47-
#define ESR_ELx_EC_DABT_LOW (0x24)
48-
#define ESR_ELx_EC_DABT_CUR (0x25)
49-
#define ESR_ELx_EC_SP_ALIGN (0x26)
50-
#define ESR_ELx_EC_MOPS (0x27)
51-
#define ESR_ELx_EC_FP_EXC32 (0x28)
47+
#define ESR_ELx_EC_DABT_LOW UL(0x24)
48+
#define ESR_ELx_EC_DABT_CUR UL(0x25)
49+
#define ESR_ELx_EC_SP_ALIGN UL(0x26)
50+
#define ESR_ELx_EC_MOPS UL(0x27)
51+
#define ESR_ELx_EC_FP_EXC32 UL(0x28)
5252
/* Unallocated EC: 0x29 - 0x2B */
53-
#define ESR_ELx_EC_FP_EXC64 (0x2C)
53+
#define ESR_ELx_EC_FP_EXC64 UL(0x2C)
5454
/* Unallocated EC: 0x2D - 0x2E */
55-
#define ESR_ELx_EC_SERROR (0x2F)
56-
#define ESR_ELx_EC_BREAKPT_LOW (0x30)
57-
#define ESR_ELx_EC_BREAKPT_CUR (0x31)
58-
#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
59-
#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
60-
#define ESR_ELx_EC_WATCHPT_LOW (0x34)
61-
#define ESR_ELx_EC_WATCHPT_CUR (0x35)
55+
#define ESR_ELx_EC_SERROR UL(0x2F)
56+
#define ESR_ELx_EC_BREAKPT_LOW UL(0x30)
57+
#define ESR_ELx_EC_BREAKPT_CUR UL(0x31)
58+
#define ESR_ELx_EC_SOFTSTP_LOW UL(0x32)
59+
#define ESR_ELx_EC_SOFTSTP_CUR UL(0x33)
60+
#define ESR_ELx_EC_WATCHPT_LOW UL(0x34)
61+
#define ESR_ELx_EC_WATCHPT_CUR UL(0x35)
6262
/* Unallocated EC: 0x36 - 0x37 */
63-
#define ESR_ELx_EC_BKPT32 (0x38)
63+
#define ESR_ELx_EC_BKPT32 UL(0x38)
6464
/* Unallocated EC: 0x39 */
65-
#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
65+
#define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */
6666
/* Unallocated EC: 0x3B */
67-
#define ESR_ELx_EC_BRK64 (0x3C)
67+
#define ESR_ELx_EC_BRK64 UL(0x3C)
6868
/* Unallocated EC: 0x3D - 0x3F */
69-
#define ESR_ELx_EC_MAX (0x3F)
69+
#define ESR_ELx_EC_MAX UL(0x3F)
7070

7171
#define ESR_ELx_EC_SHIFT (26)
7272
#define ESR_ELx_EC_WIDTH (6)

arch/arm64/include/asm/fpsimd.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -155,8 +155,6 @@ extern void cpu_enable_sme2(const struct arm64_cpu_capabilities *__unused);
155155
extern void cpu_enable_fa64(const struct arm64_cpu_capabilities *__unused);
156156
extern void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__unused);
157157

158-
extern u64 read_smcr_features(void);
159-
160158
/*
161159
* Helpers to translate bit indices in sve_vq_map to VQ values (and
162160
* vice versa). This allows find_next_bit() to be used to find the

arch/arm64/include/asm/mmu.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,6 @@ static inline bool arm64_kernel_unmapped_at_el0(void)
6363
extern void arm64_memblock_init(void);
6464
extern void paging_init(void);
6565
extern void bootmem_init(void);
66-
extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
6766
extern void create_mapping_noalloc(phys_addr_t phys, unsigned long virt,
6867
phys_addr_t size, pgprot_t prot);
6968
extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,

arch/arm64/include/asm/pgtable-hwdef.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,6 @@
135135
/*
136136
* Section
137137
*/
138-
#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
139138
#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
140139
#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
141140
#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)

arch/arm64/include/uapi/asm/sigcontext.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -320,10 +320,10 @@ struct zt_context {
320320
((sizeof(struct za_context) + (__SVE_VQ_BYTES - 1)) \
321321
/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
322322

323-
#define ZA_SIG_REGS_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
323+
#define ZA_SIG_REGS_SIZE(vq) (((vq) * __SVE_VQ_BYTES) * ((vq) * __SVE_VQ_BYTES))
324324

325325
#define ZA_SIG_ZAV_OFFSET(vq, n) (ZA_SIG_REGS_OFFSET + \
326-
(SVE_SIG_ZREG_SIZE(vq) * n))
326+
(SVE_SIG_ZREG_SIZE(vq) * (n)))
327327

328328
#define ZA_SIG_CONTEXT_SIZE(vq) \
329329
(ZA_SIG_REGS_OFFSET + ZA_SIG_REGS_SIZE(vq))
@@ -334,7 +334,7 @@ struct zt_context {
334334

335335
#define ZT_SIG_REGS_OFFSET sizeof(struct zt_context)
336336

337-
#define ZT_SIG_REGS_SIZE(n) (ZT_SIG_REG_BYTES * n)
337+
#define ZT_SIG_REGS_SIZE(n) (ZT_SIG_REG_BYTES * (n))
338338

339339
#define ZT_SIG_CONTEXT_SIZE(n) \
340340
(sizeof(struct zt_context) + ZT_SIG_REGS_SIZE(n))

arch/arm64/kernel/cpuinfo.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ const struct seq_operations cpuinfo_op = {
280280
};
281281

282282

283-
static struct kobj_type cpuregs_kobj_type = {
283+
static const struct kobj_type cpuregs_kobj_type = {
284284
.sysfs_ops = &kobj_sysfs_ops,
285285
};
286286

arch/arm64/kernel/hibernate.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -407,7 +407,7 @@ int swsusp_arch_resume(void)
407407
void *, phys_addr_t, phys_addr_t);
408408
struct trans_pgd_info trans_info = {
409409
.trans_alloc_page = hibernate_page_alloc,
410-
.trans_alloc_arg = (void *)GFP_ATOMIC,
410+
.trans_alloc_arg = (__force void *)GFP_ATOMIC,
411411
};
412412

413413
/*

0 commit comments

Comments
 (0)