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Merge tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt: "This is mostly some DT updates, but also a handful of cleanups and some fixes. The most user-visible of those are: - A device tree for the Sundance Polarberry, along with a handful of fixes and clenups to the PolarFire SOC device trees and bindings. - The memfd_secret syscall number is now visible to userspace, - Some improvements to the vm layout dump, which really should have followed shortly after the sv48 patches but I missed" * tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Move alternative length validation into subsection riscv: mm: init: make pt_ops_set_[early|late|fixmap] static riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild RISC-V: Mark IORESOURCE_EXCLUSIVE for reserved mem instead of IORESOURCE_BUSY riscv: Wire up memfd_secret in UAPI header riscv: Fix irq_work when SMP is disabled riscv: Improve virtual kernel memory layout dump riscv: Initialize thread pointer before calling C functions Documentation: riscv: Add sv48 description to VM layout RISC-V: Only default to spinwait on SBI-0.1 and M-mode riscv: dts: icicle: sort nodes alphabetically riscv: microchip: icicle: readability fixes riscv: dts: microchip: add the sundance polarberry dt-bindings: riscv: microchip: add polarberry compatible string dt-bindings: vendor-prefixes: add Sundance DSP riscv: dts: microchip: make the fabric dtsi board specific dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: remove soc vendor from filenames riscv: dts: microchip: move sysctrlr out of soc bus riscv: dts: microchip: remove icicle memory clocks
2 parents 4ab6cfc + 61114e7 commit f66e797

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‎Documentation/devicetree/bindings/riscv/microchip.yaml

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@@ -20,6 +20,8 @@ properties:
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items:
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- enum:
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- microchip,mpfs-icicle-kit
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- microchip,mpfs-icicle-reference-rtlv2203
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- sundance,polarberry
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- const: microchip,mpfs
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additionalProperties: true

‎Documentation/devicetree/bindings/vendor-prefixes.yaml

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@@ -1207,6 +1207,8 @@ patternProperties:
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description: Summit microelectronics
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"^sunchip,.*":
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description: Shenzhen Sunchip Technology Co., Ltd
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"^sundance,.*":
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description: Sundance DSP Inc.
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"^sunplus,.*":
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description: Sunplus Technology Co., Ltd.
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"^SUNW,.*":

‎Documentation/riscv/vm-layout.rst

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@@ -61,3 +61,39 @@ RISC-V Linux Kernel SV39
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ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
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ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
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__________________|____________|__________________|_________|____________________________________________________________
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65+
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RISC-V Linux Kernel SV48
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------------------------
68+
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::
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========================================================================================================================
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Start addr | Offset | End addr | Size | VM area description
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========================================================================================================================
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| | | |
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0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different per mm
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__________________|____________|__________________|_________|___________________________________________________________
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| | | |
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0000800000000000 | +128 TB | ffff7fffffffffff | ~16M TB | ... huge, almost 64 bits wide hole of non-canonical
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| | | | virtual memory addresses up to the -128 TB
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| | | | starting offset of kernel mappings.
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__________________|____________|__________________|_________|___________________________________________________________
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|
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| Kernel-space virtual memory, shared between all processes:
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____________________________________________________________|___________________________________________________________
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| | | |
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ffff8d7ffee00000 | -114.5 TB | ffff8d7ffeffffff | 2 MB | fixmap
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ffff8d7fff000000 | -114.5 TB | ffff8d7fffffffff | 16 MB | PCI io
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ffff8d8000000000 | -114.5 TB | ffff8f7fffffffff | 2 TB | vmemmap
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ffff8f8000000000 | -112.5 TB | ffffaf7fffffffff | 32 TB | vmalloc/ioremap space
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ffffaf8000000000 | -80.5 TB | ffffef7fffffffff | 64 TB | direct mapping of all physical memory
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ffffef8000000000 | -16.5 TB | fffffffeffffffff | 16.5 TB | kasan
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__________________|____________|__________________|_________|____________________________________________________________
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|
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| Identical layout to the 39-bit one from here on:
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____________________________________________________________|____________________________________________________________
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| | | |
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ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
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ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
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__________________|____________|__________________|_________|____________________________________________________________

‎arch/riscv/Kbuild

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@@ -2,6 +2,8 @@
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obj-y += kernel/ mm/ net/
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obj-$(CONFIG_BUILTIN_DTB) += boot/dts/
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obj-y += errata/
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obj-$(CONFIG_KVM) += kvm/
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obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += purgatory/
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‎arch/riscv/Kconfig

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@@ -396,7 +396,7 @@ config RISCV_SBI_V01
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config RISCV_BOOT_SPINWAIT
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bool "Spinwait booting method"
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depends on SMP
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default y
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default y if RISCV_SBI_V01 || RISCV_M_MODE
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help
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This enables support for booting Linux via spinwait method. In the
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spinwait method, all cores randomly jump to Linux. One of the cores
@@ -407,6 +407,12 @@ config RISCV_BOOT_SPINWAIT
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rely on ordered booting via SBI HSM extension which gets chosen
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dynamically at runtime if the firmware supports it.
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Since spinwait is incompatible with sparse hart IDs, it requires
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NR_CPUS be large enough to contain the physical hart ID of the first
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hart to enter Linux.
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If unsure what to do here, say N.
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config KEXEC
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bool "Kexec system call"
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select KEXEC_CORE

‎arch/riscv/Makefile

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@@ -103,9 +103,6 @@ endif
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head-y := arch/riscv/kernel/head.o
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106-
core-y += arch/riscv/errata/
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core-$(CONFIG_KVM) += arch/riscv/kvm/
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libs-y += arch/riscv/lib/
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libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
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‎arch/riscv/boot/dts/microchip/Makefile

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@@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
2-
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
2+
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
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obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

‎arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi renamed to ‎arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi

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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/ {
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compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
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core_pwm0: pwm@41000000 {
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compatible = "microchip,corepwm-rtl-v4";
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reg = <0x0 0x41000000 0x0 0xF0>;

‎arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts renamed to ‎arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts

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/dts-v1/;
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#include "microchip-mpfs.dtsi"
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#include "mpfs.dtsi"
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#include "mpfs-icicle-kit-fabric.dtsi"
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
@@ -32,41 +33,71 @@
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x2e000000>;
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clocks = <&clkcfg CLK_DDRC>;
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status = "okay";
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};
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3939
ddrc_cache_hi: memory@1000000000 {
4040
device_type = "memory";
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reg = <0x10 0x0 0x0 0x40000000>;
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clocks = <&clkcfg CLK_DDRC>;
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status = "okay";
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};
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};
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47-
&refclk {
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clock-frequency = <125000000>;
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&core_pwm0 {
47+
status = "okay";
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};
5049

51-
&mmuart1 {
50+
&gpio2 {
51+
interrupts = <53>, <53>, <53>, <53>,
52+
<53>, <53>, <53>, <53>,
53+
<53>, <53>, <53>, <53>,
54+
<53>, <53>, <53>, <53>,
55+
<53>, <53>, <53>, <53>,
56+
<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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status = "okay";
5360
};
5461

55-
&mmuart2 {
62+
&i2c0 {
5663
status = "okay";
5764
};
5865

59-
&mmuart3 {
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&i2c1 {
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status = "okay";
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};
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63-
&mmuart4 {
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&i2c2 {
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status = "okay";
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};
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67-
&mmc {
74+
&mac0 {
75+
phy-mode = "sgmii";
76+
phy-handle = <&phy0>;
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status = "okay";
78+
};
79+
80+
&mac1 {
81+
phy-mode = "sgmii";
82+
phy-handle = <&phy1>;
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status = "okay";
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85+
phy1: ethernet-phy@9 {
86+
reg = <9>;
87+
ti,fifo-depth = <0x1>;
88+
};
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90+
phy0: ethernet-phy@8 {
91+
reg = <8>;
92+
ti,fifo-depth = <0x1>;
93+
};
94+
};
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96+
&mbox {
97+
status = "okay";
98+
};
99+
100+
&mmc {
70101
bus-width = <4>;
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disable-wp;
72103
cap-sd-highspeed;
@@ -78,84 +109,54 @@
78109
sd-uhs-sdr25;
79110
sd-uhs-sdr50;
80111
sd-uhs-sdr104;
81-
};
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83-
&spi0 {
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status = "okay";
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};
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87-
&spi1 {
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&mmuart1 {
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status = "okay";
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};
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91-
&qspi {
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&mmuart2 {
92120
status = "okay";
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};
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95-
&i2c0 {
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&mmuart3 {
96124
status = "okay";
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};
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99-
&i2c1 {
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&mmuart4 {
100128
status = "okay";
101129
};
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103-
&i2c2 {
131+
&pcie {
104132
status = "okay";
105133
};
106134

107-
&mac0 {
108-
phy-mode = "sgmii";
109-
phy-handle = <&phy0>;
110-
};
111-
112-
&mac1 {
135+
&qspi {
113136
status = "okay";
114-
phy-mode = "sgmii";
115-
phy-handle = <&phy1>;
116-
phy1: ethernet-phy@9 {
117-
reg = <9>;
118-
ti,fifo-depth = <0x1>;
119-
};
120-
phy0: ethernet-phy@8 {
121-
reg = <8>;
122-
ti,fifo-depth = <0x1>;
123-
};
124137
};
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126-
&gpio2 {
127-
interrupts = <53>, <53>, <53>, <53>,
128-
<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
131-
<53>, <53>, <53>, <53>,
132-
<53>, <53>, <53>, <53>,
133-
<53>, <53>, <53>, <53>,
134-
<53>, <53>, <53>, <53>;
135-
status = "okay";
139+
&refclk {
140+
clock-frequency = <125000000>;
136141
};
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138143
&rtc {
139144
status = "okay";
140145
};
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142-
&usb {
147+
&spi0 {
143148
status = "okay";
144-
dr_mode = "host";
145149
};
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&mbox {
151+
&spi1 {
148152
status = "okay";
149153
};
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151155
&syscontroller {
152156
status = "okay";
153157
};
154158

155-
&pcie {
156-
status = "okay";
157-
};
158-
159-
&core_pwm0 {
159+
&usb {
160160
status = "okay";
161+
dr_mode = "host";
161162
};

‎arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi

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1+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2+
/* Copyright (c) 2020-2022 Microchip Technology Inc */
3+
4+
/ {
5+
fabric_clk3: fabric-clk3 {
6+
compatible = "fixed-clock";
7+
#clock-cells = <0>;
8+
clock-frequency = <62500000>;
9+
};
10+
11+
fabric_clk1: fabric-clk1 {
12+
compatible = "fixed-clock";
13+
#clock-cells = <0>;
14+
clock-frequency = <125000000>;
15+
};
16+
};

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